Simulation Results: rstmgr

 
04/08/2026 19:57:32 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.68 %
  • code
  • 99.21 %
  • assert
  • 98.35 %
  • func
  • 95.48 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.41 %
  • toggle
  • 99.52 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.650s 62.302us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.230s 92.701us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.250s 38.454us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.610s 235.384us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.100s 37.441us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.360s 99.378us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.250s 38.454us 1 1 100.00
rstmgr_csr_aliasing 1.100s 37.441us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.720s 178.190us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.230s 38.553us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.150s 55.290us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.500s 575.857us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.500s 575.857us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.500s 575.857us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.500s 575.857us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 13.730s 2075.362us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.250s 40.849us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.580s 57.244us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.580s 57.244us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.230s 92.701us 1 1 100.00
rstmgr_csr_rw 1.250s 38.454us 1 1 100.00
rstmgr_csr_aliasing 1.100s 37.441us 1 1 100.00
rstmgr_same_csr_outstanding 1.210s 75.769us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.230s 92.701us 1 1 100.00
rstmgr_csr_rw 1.250s 38.454us 1 1 100.00
rstmgr_csr_aliasing 1.100s 37.441us 1 1 100.00
rstmgr_same_csr_outstanding 1.210s 75.769us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 17.580s 3694.436us 1 1 100.00
rstmgr_tl_intg_err 7.450s 1108.976us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 17.580s 3694.436us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 17.580s 3694.436us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 7.450s 1108.976us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.380s 62.101us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.090s 483.811us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.920s 291.640us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 17.580s 3694.436us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.250s 38.454us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.250s 38.454us 1 1 100.00