Simulation Results: rv_dm/use_dmi_interface

 
04/08/2026 19:57:32 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.66 %
  • code
  • 73.41 %
  • assert
  • 96.66 %
  • func
  • 92.90 %
  • block
  • 89.69 %
  • line
  • 89.52 %
  • branch
  • 72.02 %
  • toggle
  • 71.40 %
  • FSM
  • 60.71 %
Validation stages
V1
96.30%
V2
69.57%
V2S
85.71%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 31.000s 2689.292us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 33.000s 635.967us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 30.000s 1140.587us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 31.000s 3267.115us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 32.000s 480.386us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 46.000s 13895.927us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 35.000s 3868.846us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 64.000s 26514.877us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 96.000s 57004.771us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 32.000s 256.565us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 31.000s 325.438us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 33.000s 211.409us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 33.000s 175.168us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 31.000s 96.972us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 33.000s 1332.241us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 31.000s 100.477us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 32.000s 629.107us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 32.000s 256.565us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 31.000s 571.976us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 32.000s 247.096us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 33.000s 211.409us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 30.000s 75.922us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 31.000s 166.845us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 30.000s 146.164us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 63.000s 8425.664us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 65.000s 19296.162us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_dm_csr_mem_rw_with_rand_reset 31.000s 128.971us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 65.000s 19296.162us 1 1 100.00
rv_dm_csr_rw 30.000s 146.164us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 28.000s 107.610us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 30.000s 144.442us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 31.000s 2689.292us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 33.000s 702.215us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 30.000s 292.415us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 30.000s 233.939us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 33.000s 542.817us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 50.000s 11414.663us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 31.000s 563.202us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 39.000s 5968.863us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 40.000s 6485.090us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 31.000s 253.836us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 40.000s 5582.961us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 30.000s 568.797us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 31.000s 194.842us 0 1 0.00
tap_ctrl_transitions 2 2 100.00
rv_dm_tap_fsm 33.000s 10186.376us 1 1 100.00
rv_dm_tap_fsm_rand_reset 48.000s 8380.128us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 30.000s 65.178us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 31.000s 2485.286us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 30.000s 90.538us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_dm_tl_errors 36.000s 400.169us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_dm_tl_errors 36.000s 400.169us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 65.000s 19296.162us 1 1 100.00
rv_dm_csr_hw_reset 31.000s 166.845us 1 1 100.00
rv_dm_csr_rw 30.000s 146.164us 1 1 100.00
rv_dm_same_csr_outstanding 37.000s 677.652us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 65.000s 19296.162us 1 1 100.00
rv_dm_csr_hw_reset 31.000s 166.845us 1 1 100.00
rv_dm_csr_rw 30.000s 146.164us 1 1 100.00
rv_dm_same_csr_outstanding 37.000s 677.652us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_sec_cm 31.000s 878.603us 1 1 100.00
rv_dm_tl_intg_err 36.000s 2967.070us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 36.000s 2967.070us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 40.000s 5582.961us 1 1 100.00
rv_dm_debug_disabled 30.000s 224.731us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 40.000s 5582.961us 1 1 100.00
rv_dm_debug_disabled 30.000s 224.731us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 31.000s 2689.292us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 0 1 0.00
rv_dm_buffered_enable 32.000s 600.091us 0 1 0.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 31.000s 55.835us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 31.000s 55.835us 1 1 100.00
sec_cm_exec_ctrl_mubi 0 1 0.00
rv_dm_buffered_enable 32.000s 600.091us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 50.000s 14834.307us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 106.000s 300000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared: 3 test runs
rv_dm_sba_tl_access 32772318282600454766394264093374894101147897121588962597648043911884705983649 87
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23926
rv_dm_bad_sba_tl_access 11121901062819140963047321550667317938572370680027875274379584030377647309873 87
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23833
rv_dm_autoincr_sba_tl_access 4604859910389865545761749121131843776202917705151027799103441013359865330768 135
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23902
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == *'b* (* [*] vs * [*]) 2 test runs
rv_dm_mem_tl_access_resuming 71819603543001039842007843833454862448438332609361248517425782145712602491274 87
UVM_INFO @ 175168393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 50526088624743671637507306167567253111559179639158051517342177825948316790156 120
UVM_INFO @ 14834306798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) 2 test runs
rv_dm_jtag_dmi_debug_disabled 13457344830128675387996964742978090258824290150975993548470177929570652191260 87
UVM_INFO @ 253835725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 110775123007502692126793806224783279345495058284995841046628449173918321366679 91
UVM_INFO @ 2485286136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp 1 test run
rv_dm_delayed_resp_sba_tl_access 8528596420124932205555821346843462705878513014953848478401784170944752521025 107
UVM_INFO @ 563202088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [*] vs * [*]) 1 test run
rv_dm_hart_unavail 46352626912546109535620027476201896115494183564122976421124079056851648791924 87
UVM_INFO @ 194842073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [*] vs * [*]) 1 test run
rv_dm_buffered_enable 93328206422113099431648306162412265732625981302754959442145844243582318086412 89
UVM_INFO @ 600091285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
rv_dm_scanmode 59265914840915324959955750391474591537739234966794457644385823926293499477564 87
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---