Simulation Results: spi_host

 
04/08/2026 19:57:32 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.23 %
  • code
  • 91.30 %
  • assert
  • 94.14 %
  • func
  • 88.24 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 23.000s 2855.575us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 37.253us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 61.553us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 4.000s 579.661us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 233.311us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 25.743us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 61.553us 1 1 100.00
spi_host_csr_aliasing 2.000s 233.311us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 20.550us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 79.956us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 23.036us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 54.770us 1 1 100.00
spi_host_error_cmd 1.000s 21.203us 1 1 100.00
spi_host_event 9.000s 5481.084us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 1.000s 98.376us 1 1 100.00
speed 1 1 100.00
spi_host_speed 1.000s 98.376us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 1.000s 98.376us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 171.000s 10975.065us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 61.000s 2608.308us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 98.014us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 1.000s 98.376us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 1.000s 98.376us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 23.000s 2855.575us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 23.000s 2855.575us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 3.000s 388.095us 1 1 100.00
spien 1 1 100.00
spi_host_spien 5.000s 512.947us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 19.000s 1761.507us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 96.710us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 54.770us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 113.099us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 16.109us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 234.549us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 234.549us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 37.253us 1 1 100.00
spi_host_csr_rw 1.000s 61.553us 1 1 100.00
spi_host_csr_aliasing 2.000s 233.311us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 108.080us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 37.253us 1 1 100.00
spi_host_csr_rw 1.000s 61.553us 1 1 100.00
spi_host_csr_aliasing 2.000s 233.311us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 108.080us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 84.952us 1 1 100.00
spi_host_sec_cm 1.000s 248.972us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 84.952us 1 1 100.00