Simulation Results: sram_ctrl/main

 
04/08/2026 19:57:32 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.75 %
  • code
  • 95.75 %
  • assert
  • 97.69 %
  • func
  • 93.80 %
  • block
  • 96.16 %
  • line
  • 96.82 %
  • branch
  • 94.32 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 1886.384us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 21.876us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 19.215us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 391.056us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 42.772us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 1319.608us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 19.215us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 42.772us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 195.000s 6156.027us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 52.000s 10697.379us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 11.000s 2558.919us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 191.000s 23636.651us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 123.000s 5154.032us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 44.000s 43017.094us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 31.000s 42156.448us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 23.000s 10254.760us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 357.476us 1 1 100.00
sram_ctrl_partial_access_b2b 215.000s 78097.399us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 3.000s 1761.068us 1 1 100.00
sram_ctrl_throughput_w_partial_write 7.000s 5125.287us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 1558.328us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 7.000s 725.637us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 696.165us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 54.000s 12518.743us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 20.755us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 164.249us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 164.249us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 21.876us 1 1 100.00
sram_ctrl_csr_rw 1.000s 19.215us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 42.772us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 22.088us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 21.876us 1 1 100.00
sram_ctrl_csr_rw 1.000s 19.215us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 42.772us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 22.088us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 24.000s 44068.739us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 1412.803us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 153.424us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 1412.803us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 153.424us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 725.637us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 725.637us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 19.215us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 23.000s 10254.760us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 23.000s 10254.760us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 23.000s 10254.760us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 31.000s 42156.448us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 2669.661us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 24.000s 44068.739us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 6.000s 6642.574us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 1886.384us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 1886.384us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 23.000s 10254.760us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 1412.803us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 31.000s 42156.448us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 1412.803us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1412.803us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 1886.384us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1412.803us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 15.000s 901.951us 1 1 100.00