Simulation Results: uart

 
04/08/2026 19:57:32 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.72 %
  • code
  • 92.48 %
  • assert
  • 97.98 %
  • func
  • 90.69 %
  • block
  • 98.83 %
  • line
  • 99.24 %
  • branch
  • 97.79 %
  • toggle
  • 72.91 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.000s 332.167us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 18.039us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 13.676us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.000s 90.002us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 249.712us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 2.000s 78.641us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 13.676us 1 1 100.00
uart_csr_aliasing 1.000s 249.712us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 38.000s 35356.279us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.000s 332.167us 1 1 100.00
uart_tx_rx 38.000s 35356.279us 1 1 100.00
parity_error 2 2 100.00
uart_intr 52.000s 38372.400us 1 1 100.00
uart_rx_parity_err 126.000s 107199.898us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 38.000s 35356.279us 1 1 100.00
uart_intr 52.000s 38372.400us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 116.000s 146658.981us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 79.000s 94003.106us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 198.000s 279000.819us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 52.000s 38372.400us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 52.000s 38372.400us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 52.000s 38372.400us 1 1 100.00
perf 1 1 100.00
uart_perf 44.000s 9758.643us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 4.000s 1628.677us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 4.000s 1628.677us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 7.000s 4955.512us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 6.000s 1834.588us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 4.000s 972.098us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 16.000s 6146.583us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 264.000s 216597.407us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 429.000s 314686.781us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 11.396us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 17.914us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 123.877us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 123.877us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 18.039us 1 1 100.00
uart_csr_rw 1.000s 13.676us 1 1 100.00
uart_csr_aliasing 1.000s 249.712us 1 1 100.00
uart_same_csr_outstanding 1.000s 63.754us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 18.039us 1 1 100.00
uart_csr_rw 1.000s 13.676us 1 1 100.00
uart_csr_aliasing 1.000s 249.712us 1 1 100.00
uart_same_csr_outstanding 1.000s 63.754us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 2.000s 553.873us 1 1 100.00
uart_tl_intg_err 2.000s 183.002us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 2.000s 183.002us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 15.000s 3417.964us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:379) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 1 test run
uart_noise_filter 15752789837276208837476799659861255291328597739185426474767975068890755883559 87
UVM_ERROR @ 4865391830 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 4865391830 ps: (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 4872551830 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 11
UVM_ERROR @ 4872571830 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty