Simulation Results: alert_handler

 
05/08/2026 19:49:27 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.47 %
  • code
  • 90.34 %
  • assert
  • 98.29 %
  • func
  • 76.78 %
  • line
  • 99.71 %
  • branch
  • 98.20 %
  • cond
  • 91.46 %
  • toggle
  • 88.15 %
  • FSM
  • 74.19 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 19.380s 574.737us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 2.760s 81.938us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 4.510s 71.699us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 217.520s 10240.506us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 258.680s 42199.839us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 6.480s 390.990us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 4.510s 71.699us 1 1 100.00
alert_handler_csr_aliasing 258.680s 42199.839us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 58.710s 6781.219us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 26.870s 8197.837us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1716.120s 84806.098us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 23.480s 1296.946us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 19.380s 574.737us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 46.020s 20399.465us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 25.020s 1041.909us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 328.660s 78557.150us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 1225.040s 89047.261us 1 1 100.00
alert_handler_lpg_stub_clk 1767.910s 43539.170us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 97.740s 6551.928us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 9.080s 250.793us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 3.460s 116.559us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.490s 19.943us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 19.530s 616.912us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 19.530s 616.912us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 2.760s 81.938us 1 1 100.00
alert_handler_csr_rw 4.510s 71.699us 1 1 100.00
alert_handler_csr_aliasing 258.680s 42199.839us 1 1 100.00
alert_handler_same_csr_outstanding 16.220s 196.223us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 2.760s 81.938us 1 1 100.00
alert_handler_csr_rw 4.510s 71.699us 1 1 100.00
alert_handler_csr_aliasing 258.680s 42199.839us 1 1 100.00
alert_handler_same_csr_outstanding 16.220s 196.223us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 142.400s 19549.318us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 142.400s 19549.318us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 142.400s 19549.318us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 142.400s 19549.318us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 488.520s 20470.893us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 10.080s 939.047us 1 1 100.00
alert_handler_tl_intg_err 32.730s 1020.906us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 32.730s 1020.906us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 142.400s 19549.318us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 19.380s 574.737us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 19.380s 574.737us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 19.380s 574.737us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 19.380s 574.737us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 23.480s 1296.946us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1225.040s 89047.261us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 23.480s 1296.946us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1716.120s 84806.098us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1716.120s 84806.098us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 10.080s 939.047us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 10.080s 939.047us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 10.080s 939.047us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 10.080s 939.047us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 10.080s 939.047us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 10.080s 939.047us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 10.080s 939.047us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 10.080s 939.047us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 10.080s 939.047us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 25.100s 3490.822us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 103173401285566603765934087276053070979255036703229229878251218712395042946630 216
UVM_INFO @ 250792940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 81605629987970907192255516908642086672600532771850976592526394195366452825241 83
UVM_INFO @ 3490822132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---