Simulation Results: clkmgr

 
05/08/2026 19:49:27 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.66 %
  • code
  • 68.72 %
  • assert
  • 89.67 %
  • func
  • 62.60 %
  • line
  • 81.56 %
  • branch
  • 86.53 %
  • cond
  • 78.42 %
  • toggle
  • 97.08 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
53.85%
V2S
25.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.870s 23.192us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.070s 45.820us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.760s 3.863us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 5.020s 449.370us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.920s 28.770us 0 1 0.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.190s 63.579us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.760s 3.863us 0 1 0.00
clkmgr_csr_aliasing 0.920s 28.770us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.750s 14.001us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.310s 76.607us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.000s 23.465us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.870s 23.192us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.880s 38.716us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.610s 3.376us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.880s 38.716us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.680s 5.133us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.560s 48.645us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.130s 37.095us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.130s 37.095us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 1.070s 45.820us 1 1 100.00
clkmgr_csr_rw 0.760s 3.863us 0 1 0.00
clkmgr_csr_aliasing 0.920s 28.770us 0 1 0.00
clkmgr_same_csr_outstanding 0.730s 7.408us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 1.070s 45.820us 1 1 100.00
clkmgr_csr_rw 0.760s 3.863us 0 1 0.00
clkmgr_csr_aliasing 0.920s 28.770us 0 1 0.00
clkmgr_same_csr_outstanding 0.730s 7.408us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 1.520s 98.743us 0 1 0.00
clkmgr_tl_intg_err 0.690s 4.788us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.170s 53.195us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.170s 53.195us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.170s 53.195us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.170s 53.195us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.710s 10.744us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.690s 4.788us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.880s 38.716us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.610s 3.376us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.170s 53.195us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.100s 60.288us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.760s 3.863us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.520s 98.743us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.760s 3.863us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.760s 3.863us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.520s 98.743us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.690s 3.680us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.050s 29.643us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 3 test runs
clkmgr_shadow_reg_errors_with_csr_rw 3994594688802657923084124310961476673385062718724480081916730167139171381499 75
UVM_INFO @ 10744122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 96649609039035915131854594416310000930647848488672942810886391441523434241444 79
UVM_INFO @ 4788292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 44968472742207874163558823411127526891817288202441017163265656621704435678790 75
UVM_INFO @ 28769658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 109968916267171066071804484093572433172959274206410325925542115672473091609182 76
UVM_INFO @ 38715588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 91956736524684911958973949025405119159347900820815665416916126395680901484043 84
UVM_INFO @ 29643366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 28022719261786250532738232886148880725703792852330010085477204236091206211985 78
UVM_INFO @ 3375983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 70541193525600946559854047849172932782214208506485338770841528322169218578208 78
UVM_INFO @ 5133254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 57289583529598345839901439866652922408598943128079146438281823977344700903001 74
UVM_INFO @ 3680194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 18228828977101944296140153784043049602622627933620520744422470528820141646947 104
UVM_INFO @ 98742647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 1 test run
clkmgr_csr_rw 12176109268078931272797677083091813881165038119801565181470872531497779681209 75
UVM_INFO @ 3862605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 110938952674227319518715462904528595519629463547047443498944181580741509205528 75
UVM_INFO @ 449369953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 100486325922298783213078134309488938956183210229674148559602446328975639851499 76
UVM_INFO @ 7408056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---