Simulation Results: dma

 
05/08/2026 19:49:27 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.41 %
  • code
  • 90.41 %
  • assert
  • 96.61 %
  • func
  • 63.20 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 77.37 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 1447.861us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 6.000s 339.019us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 553.101us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 61.595us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 15.388us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 5.000s 232.531us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 5.000s 585.079us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 44.234us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 15.388us 1 1 100.00
dma_csr_aliasing 5.000s 585.079us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 27.000s 26565.664us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 303.000s 67215.785us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 85.000s 24142.368us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 85.000s 24142.368us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 303.000s 67215.785us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 214.000s 180938.548us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 85.000s 24142.368us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 6.000s 860.938us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 211.000s 43760.286us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 12.457us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 40.600us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 923.406us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 923.406us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 61.595us 1 1 100.00
dma_csr_rw 1.000s 15.388us 1 1 100.00
dma_csr_aliasing 5.000s 585.079us 1 1 100.00
dma_same_csr_outstanding 2.000s 210.652us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 61.595us 1 1 100.00
dma_csr_rw 1.000s 15.388us 1 1 100.00
dma_csr_aliasing 5.000s 585.079us 1 1 100.00
dma_same_csr_outstanding 2.000s 210.652us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 17.000s 784.100us 1 1 100.00
dma_generic_stress 214.000s 180938.548us 1 1 100.00
dma_handshake_stress 85.000s 24142.368us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 8.000s 320.534us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 3.000s 442.281us 1 1 100.00
dma_sec_cm 1.000s 41.777us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 96.000s 34933.197us 1 1 100.00
dma_longer_transfer 2.000s 79.459us 1 1 100.00
dma_stress_all_with_rand_reset 3.000s 430.045us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 71793950614867373532550083319824220764868970950170920716980186586784897581158 91
UVM_INFO @ 430045252ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---