Simulation Results: edn/edn0

 
05/08/2026 19:49:27 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 77.58 %
  • code
  • 86.72 %
  • assert
  • 96.24 %
  • func
  • 49.79 %
  • block
  • 94.51 %
  • line
  • 97.27 %
  • branch
  • 88.10 %
  • toggle
  • 76.24 %
  • FSM
  • 85.27 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 45.637us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 42.766us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 29.507us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.000s 219.649us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.000s 48.568us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 24.506us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 29.507us 1 1 100.00
edn_csr_aliasing 1.000s 48.568us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 93.142us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 93.142us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 93.142us 1 1 100.00
interrupts 1 1 100.00
edn_intr 2.000s 44.878us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.000s 29.468us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 29.807us 1 1 100.00
disable 2 2 100.00
edn_disable 2.000s 41.356us 1 1 100.00
edn_disable_auto_req_mode 1.000s 71.707us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 9.000s 240.632us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.000s 37.346us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.000s 21.034us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.000s 33.712us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.000s 33.712us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 42.766us 1 1 100.00
edn_csr_rw 2.000s 29.507us 1 1 100.00
edn_csr_aliasing 1.000s 48.568us 1 1 100.00
edn_same_csr_outstanding 1.000s 39.443us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 42.766us 1 1 100.00
edn_csr_rw 2.000s 29.507us 1 1 100.00
edn_csr_aliasing 1.000s 48.568us 1 1 100.00
edn_same_csr_outstanding 1.000s 39.443us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.000s 991.476us 1 1 100.00
edn_tl_intg_err 3.000s 180.428us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.000s 18.467us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.000s 29.468us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.000s 991.476us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.000s 991.476us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.000s 991.476us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.000s 991.476us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.000s 29.468us 1 1 100.00
edn_sec_cm 7.000s 991.476us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.000s 29.468us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.000s 180.428us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 76.000s 11653.626us 1 1 100.00