Simulation Results: edn/edn1

 
05/08/2026 19:49:27 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.37 %
  • code
  • 83.25 %
  • assert
  • 97.14 %
  • func
  • 81.72 %
  • line
  • 98.18 %
  • branch
  • 93.29 %
  • cond
  • 90.38 %
  • toggle
  • 87.80 %
  • FSM
  • 46.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.860s 17.711us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.790s 13.403us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.010s 30.464us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.600s 2096.995us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.130s 21.455us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.330s 72.945us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.010s 30.464us 1 1 100.00
edn_csr_aliasing 1.130s 21.455us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.190s 190.710us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.190s 190.710us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.190s 190.710us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.910s 52.349us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.010s 113.178us 1 1 100.00
errs 1 1 100.00
edn_err 1.040s 29.365us 1 1 100.00
disable 2 2 100.00
edn_disable 0.760s 33.633us 1 1 100.00
edn_disable_auto_req_mode 1.020s 448.069us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 0.790s 32.871us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.760s 25.386us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.850s 31.437us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.130s 86.821us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.130s 86.821us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.790s 13.403us 1 1 100.00
edn_csr_rw 1.010s 30.464us 1 1 100.00
edn_csr_aliasing 1.130s 21.455us 1 1 100.00
edn_same_csr_outstanding 1.030s 104.918us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.790s 13.403us 1 1 100.00
edn_csr_rw 1.010s 30.464us 1 1 100.00
edn_csr_aliasing 1.130s 21.455us 1 1 100.00
edn_same_csr_outstanding 1.030s 104.918us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.910s 506.543us 1 1 100.00
edn_tl_intg_err 2.320s 362.434us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.870s 56.779us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.010s 113.178us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.910s 506.543us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.910s 506.543us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.910s 506.543us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.910s 506.543us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.010s 113.178us 1 1 100.00
edn_sec_cm 4.910s 506.543us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.010s 113.178us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.320s 362.434us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 23.870s 10075.169us 1 1 100.00