Simulation Results: entropy_src/rng_16bits

 
05/08/2026 19:49:27 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 70.03 %
  • code
  • 82.82 %
  • assert
  • 74.20 %
  • func
  • 53.06 %
  • block
  • 94.10 %
  • line
  • 97.73 %
  • branch
  • 86.22 %
  • toggle
  • 52.53 %
  • FSM
  • 94.79 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 119.627us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 72.146us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 78.703us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 15.000s 2044.578us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 4.000s 378.737us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 2.000s 56.956us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 78.703us 1 1 100.00
entropy_src_csr_aliasing 4.000s 378.737us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 119.627us 1 1 100.00
entropy_src_rng 289.000s 13046.496us 1 1 100.00
entropy_src_fw_ov 160.000s 13036.501us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 160.000s 13036.501us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 289.000s 13046.496us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 463.000s 13060.328us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 289.000s 13046.496us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 289.000s 13046.496us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 289.000s 13046.496us 1 1 100.00
entropy_src_intr 18.000s 801.085us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 289.000s 13046.496us 1 1 100.00
entropy_src_functional_alerts 5.000s 182.861us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 2.000s 70.117us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 64.464us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 2.000s 125.805us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 1.000s 52.327us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 50.488us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 5.000s 165.959us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 5.000s 165.959us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 72.146us 1 1 100.00
entropy_src_csr_rw 2.000s 78.703us 1 1 100.00
entropy_src_csr_aliasing 4.000s 378.737us 1 1 100.00
entropy_src_same_csr_outstanding 1.000s 94.784us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 72.146us 1 1 100.00
entropy_src_csr_rw 2.000s 78.703us 1 1 100.00
entropy_src_csr_aliasing 4.000s 378.737us 1 1 100.00
entropy_src_same_csr_outstanding 1.000s 94.784us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 96.649us 1 1 100.00
entropy_src_tl_intg_err 4.000s 136.154us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 289.000s 13046.496us 1 1 100.00
entropy_src_cfg_regwen 2.000s 22.769us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 289.000s 13046.496us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 289.000s 13046.496us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 289.000s 13046.496us 1 1 100.00
entropy_src_fw_ov 160.000s 13036.501us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 64.464us 1 1 100.00
entropy_src_sec_cm 2.000s 96.649us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 64.464us 1 1 100.00
entropy_src_sec_cm 2.000s 96.649us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 289.000s 13046.496us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 64.464us 1 1 100.00
entropy_src_sec_cm 2.000s 96.649us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 64.464us 1 1 100.00
entropy_src_sec_cm 2.000s 96.649us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 64.464us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 5.000s 182.861us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 4.000s 136.154us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 23.000s 15106.729us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 18.000s 2353.967us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_hi_threshold 1 test run
entropy_src_stress_all_with_rand_reset 72670559166183305994319788113019916181770948592389652406781364867332855246542 1136
UVM_INFO @ 2353967045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror alert_fail_counts 1 test run
entropy_src_csr_mem_rw_with_rand_reset 94916466844466357923614796246646550806034339506822588702929283963248177344103 113
UVM_INFO @ 56955952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---