Simulation Results: hmac

 
05/08/2026 19:49:27 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.09 %
  • code
  • 96.03 %
  • assert
  • 97.17 %
  • func
  • 29.06 %
  • block
  • 97.55 %
  • line
  • 98.44 %
  • branch
  • 93.88 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 2.000s 426.845us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 170.683us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 186.803us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.000s 471.247us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.000s 192.776us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 13.326us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 186.803us 1 1 100.00
hmac_csr_aliasing 3.000s 192.776us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 54.000s 11565.740us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 2.000s 132.753us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 197.000s 9895.597us 1 1 100.00
hmac_test_sha384_vectors 384.000s 31574.282us 1 1 100.00
hmac_test_sha512_vectors 21.000s 1222.732us 1 1 100.00
hmac_test_hmac256_vectors 7.000s 1141.760us 1 1 100.00
hmac_test_hmac384_vectors 11.000s 893.314us 1 1 100.00
hmac_test_hmac512_vectors 12.000s 383.018us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 8.000s 1104.409us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 247.000s 52553.452us 1 1 100.00
error 1 1 100.00
hmac_error 40.000s 8239.032us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 127.000s 12975.976us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 2.000s 426.845us 1 1 100.00
hmac_long_msg 54.000s 11565.740us 1 1 100.00
hmac_back_pressure 2.000s 132.753us 1 1 100.00
hmac_datapath_stress 247.000s 52553.452us 1 1 100.00
hmac_burst_wr 8.000s 1104.409us 1 1 100.00
hmac_stress_all 1.000s 90.077us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 2.000s 426.845us 1 1 100.00
hmac_long_msg 54.000s 11565.740us 1 1 100.00
hmac_back_pressure 2.000s 132.753us 1 1 100.00
hmac_datapath_stress 247.000s 52553.452us 1 1 100.00
hmac_wipe_secret 127.000s 12975.976us 1 1 100.00
hmac_test_sha256_vectors 197.000s 9895.597us 1 1 100.00
hmac_test_sha384_vectors 384.000s 31574.282us 1 1 100.00
hmac_test_sha512_vectors 21.000s 1222.732us 1 1 100.00
hmac_test_hmac256_vectors 7.000s 1141.760us 1 1 100.00
hmac_test_hmac384_vectors 11.000s 893.314us 1 1 100.00
hmac_test_hmac512_vectors 12.000s 383.018us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 2.000s 426.845us 1 1 100.00
hmac_long_msg 54.000s 11565.740us 1 1 100.00
hmac_back_pressure 2.000s 132.753us 1 1 100.00
hmac_datapath_stress 247.000s 52553.452us 1 1 100.00
hmac_burst_wr 8.000s 1104.409us 1 1 100.00
hmac_error 40.000s 8239.032us 1 1 100.00
hmac_wipe_secret 127.000s 12975.976us 1 1 100.00
hmac_test_sha256_vectors 197.000s 9895.597us 1 1 100.00
hmac_test_sha384_vectors 384.000s 31574.282us 1 1 100.00
hmac_test_sha512_vectors 21.000s 1222.732us 1 1 100.00
hmac_test_hmac256_vectors 7.000s 1141.760us 1 1 100.00
hmac_test_hmac384_vectors 11.000s 893.314us 1 1 100.00
hmac_test_hmac512_vectors 12.000s 383.018us 1 1 100.00
hmac_stress_all 1.000s 90.077us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 1.000s 90.077us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 21.587us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 62.944us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.000s 228.277us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.000s 228.277us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 170.683us 1 1 100.00
hmac_csr_rw 2.000s 186.803us 1 1 100.00
hmac_csr_aliasing 3.000s 192.776us 1 1 100.00
hmac_same_csr_outstanding 2.000s 802.280us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 170.683us 1 1 100.00
hmac_csr_rw 2.000s 186.803us 1 1 100.00
hmac_csr_aliasing 3.000s 192.776us 1 1 100.00
hmac_same_csr_outstanding 2.000s 802.280us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 112.420us 1 1 100.00
hmac_tl_intg_err 3.000s 966.136us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.000s 966.136us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 2.000s 426.845us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 4.000s 349.479us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 67.000s 28932.562us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.000s 29.697us 1 1 100.00