Simulation Results: i2c

 
05/08/2026 19:49:27 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.03 %
  • code
  • 86.39 %
  • assert
  • 97.46 %
  • func
  • 80.23 %
  • block
  • 96.14 %
  • line
  • 95.62 %
  • branch
  • 93.09 %
  • toggle
  • 72.68 %
  • FSM
  • 84.17 %
Validation stages
V1
100.00%
V2
80.49%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 33.000s 4204.244us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 14.000s 742.773us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 1.000s 37.989us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 1.000s 50.653us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 5.000s 165.420us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 3.000s 119.503us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 2.000s 213.290us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 1.000s 50.653us 1 1 100.00
i2c_csr_aliasing 3.000s 119.503us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 1.000s 54.613us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 98.000s 12498.127us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 3.000s 356.612us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 1.000s 24.334us 1 1 100.00
host_fifo_watermark 0 1 0.00
i2c_host_fifo_watermark 3600.000s 0.000us 0 1 0.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 1059.000s 2030.167us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 3.000s 137.267us 1 1 100.00
i2c_host_fifo_fmt_empty 40.000s 2010.745us 1 1 100.00
i2c_host_fifo_reset_rx 4.000s 796.139us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 1050.000s 6503.900us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 31.000s 3533.991us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 3.000s 87.061us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 3.000s 399.969us 0 1 0.00
target_stress_all 0 1 0.00
i2c_target_stress_all 3600.000s 0.000us 0 1 0.00
target_maxperf 1 1 100.00
i2c_target_perf 6.000s 1050.689us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 13.000s 868.742us 1 1 100.00
i2c_target_intr_smoke 7.000s 4133.888us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 3.000s 337.876us 1 1 100.00
i2c_target_fifo_reset_tx 1.000s 298.623us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 26.000s 12387.230us 1 1 100.00
i2c_target_stress_rd 13.000s 868.742us 1 1 100.00
i2c_target_intr_stress_wr 6.000s 3772.091us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 8.000s 1243.951us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 6.000s 1769.819us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 3.000s 2096.664us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 16.000s 10201.171us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 2.000s 252.849us 1 1 100.00
i2c_target_fifo_watermarks_tx 2.000s 121.920us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 3.000s 356.612us 1 1 100.00
i2c_host_perf_precise 4.000s 75.422us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 31.000s 3533.991us 1 1 100.00
target_mode_tx_stretch_ctrl 0 1 0.00
i2c_target_tx_stretch_ctrl 2.000s 37.915us 0 1 0.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 4.000s 3386.875us 1 1 100.00
i2c_target_nack_acqfull_addr 3.000s 549.075us 1 1 100.00
i2c_target_nack_txstretch 3.000s 451.580us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 5.000s 320.675us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 4.000s 2546.410us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 1.000s 65.748us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 1.000s 54.291us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 2.000s 412.575us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 2.000s 412.575us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 1.000s 37.989us 1 1 100.00
i2c_csr_rw 1.000s 50.653us 1 1 100.00
i2c_csr_aliasing 3.000s 119.503us 1 1 100.00
i2c_same_csr_outstanding 2.000s 33.566us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 1.000s 37.989us 1 1 100.00
i2c_csr_rw 1.000s 50.653us 1 1 100.00
i2c_csr_aliasing 3.000s 119.503us 1 1 100.00
i2c_same_csr_outstanding 2.000s 33.566us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 2.000s 263.784us 1 1 100.00
i2c_sec_cm 2.000s 76.506us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 2.000s 263.784us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 4.000s 432.151us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 3.000s 391.592us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 5.000s 1205.295us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 3 test runs
i2c_host_error_intr 5478526463968422802791709311337265301250494058683340886345747241450307754299 89
UVM_INFO @ 54613199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 53490740491772969372280597787754557847487244907571295135160312825764708354872 102
UVM_INFO @ 12498127282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 102578741235135628851879614626931277848438153090590666377225211736788623847148 97
UVM_INFO @ 1205294924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 2 test runs
i2c_host_fifo_watermark 23251246600899707082187467544426549519661096703107114862362563200513429934644 None
i2c_target_stress_all 103036174452423230881038358696836859569884721036693300720178336438636325387614 None
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 39083507621503176389688358136694872797317645022253477741961373029215716074805 93
UVM_INFO @ 399968812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 48473904456425711638332274302773243585894899729753785430368706938215385860537 87
UVM_INFO @ 391592357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! 1 test run
i2c_target_hrst 101578352813353464249315252747970471876355621155472934958009593206225115315462 88
UVM_INFO @ 10201170939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
i2c_host_stress_all_with_rand_reset 46227737466443845644485781467695785732561146902839984600990613396143190203239 93
UVM_INFO @ 432151040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:629) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead 1 test run
i2c_host_mode_toggle 85187423714572002034370607520236171139733232317863870092192533733276897075934 96
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
UVM_FATAL (i2c_base_vseq.sv:882) [i2c_target_tx_stretch_ctrl_vseq] Check failed (std::randomize(transfer_lengths) with {transfer_lengths.size() == num_transfers; transfer_lengths.sum() == num_data_total; foreach (transfer_lengths[i]) { transfer_lengths[i] inside {[cfg.min_xfer_len : num_data_total]}; } transfer_lengths[*] > *; transfer_lengths[num_transfers - *] > *;}) Randomization failed! 1 test run
i2c_target_tx_stretch_ctrl 71918137935356731195833111840164061582125204642036214767466481527083396025932 112
UVM_INFO @ 37915492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---