Simulation Results: lc_ctrl/volatile_unlock_disabled

 
05/08/2026 19:49:27 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.88 %
  • code
  • 92.67 %
  • assert
  • 96.83 %
  • func
  • 86.13 %
  • block
  • 96.52 %
  • line
  • 97.23 %
  • branch
  • 91.15 %
  • toggle
  • 87.04 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 234.099us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 60.064us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 44.785us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 97.997us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 28.813us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 24.966us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 44.785us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 28.813us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 77.548us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 1376.251us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 22.502us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 57.796us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 5.000s 269.488us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.000s 794.449us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 5.000s 269.488us 1 1 100.00
lc_ctrl_prog_failure 2.000s 57.796us 1 1 100.00
lc_ctrl_errors 4.000s 794.449us 1 1 100.00
lc_ctrl_security_escalation 6.000s 1608.142us 1 1 100.00
lc_ctrl_jtag_state_failure 13.000s 6722.478us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.000s 420.671us 1 1 100.00
lc_ctrl_jtag_errors 13.000s 5713.453us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.000s 254.319us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 442.439us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.000s 420.671us 1 1 100.00
lc_ctrl_jtag_errors 13.000s 5713.453us 1 1 100.00
lc_ctrl_jtag_access 6.000s 3252.625us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.000s 3267.750us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 954.495us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 109.608us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.000s 1492.983us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.000s 3112.701us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 68.902us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 138.516us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 163.323us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.000s 217.592us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 23.319us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 111.000s 22968.053us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 29.881us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 733.856us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 733.856us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 60.064us 1 1 100.00
lc_ctrl_csr_rw 1.000s 44.785us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 28.813us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 45.720us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 60.064us 1 1 100.00
lc_ctrl_csr_rw 1.000s 44.785us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 28.813us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 45.720us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 235.585us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 328.255us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 328.255us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 1376.251us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 269.488us 1 1 100.00
lc_ctrl_sec_cm 4.000s 235.585us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 269.488us 1 1 100.00
lc_ctrl_sec_cm 4.000s 235.585us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 269.488us 1 1 100.00
lc_ctrl_sec_cm 4.000s 235.585us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.000s 269.488us 1 1 100.00
lc_ctrl_sec_cm 4.000s 235.585us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 269.488us 1 1 100.00
lc_ctrl_sec_cm 4.000s 235.585us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 269.488us 1 1 100.00
lc_ctrl_sec_cm 4.000s 235.585us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.000s 269.488us 1 1 100.00
lc_ctrl_sec_cm 4.000s 235.585us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 5.000s 269.488us 1 1 100.00
lc_ctrl_sec_cm 4.000s 235.585us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 1608.142us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 77.548us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 442.439us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 1450.277us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 1450.277us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.000s 305.128us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 552.788us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 552.788us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3.000s 534.729us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 59847828845335217345362301450433731165920820299089791912307528233008626863004 183
UVM_INFO @ 534728947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---