Simulation Results: lc_ctrl/volatile_unlock_enabled

 
05/08/2026 19:49:27 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.59 %
  • code
  • 93.00 %
  • assert
  • 95.97 %
  • func
  • 85.81 %
  • block
  • 96.98 %
  • line
  • 97.57 %
  • branch
  • 92.33 %
  • toggle
  • 86.84 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 40.571us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 17.749us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 16.153us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 203.470us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 415.533us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 33.273us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 16.153us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 415.533us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.000s 261.205us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 628.404us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 95.975us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 42.968us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.000s 1428.644us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.000s 289.329us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.000s 1428.644us 1 1 100.00
lc_ctrl_prog_failure 2.000s 42.968us 1 1 100.00
lc_ctrl_errors 4.000s 289.329us 1 1 100.00
lc_ctrl_security_escalation 4.000s 979.723us 1 1 100.00
lc_ctrl_jtag_state_failure 20.000s 2682.494us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 280.942us 1 1 100.00
lc_ctrl_jtag_errors 14.000s 2184.314us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.000s 345.832us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3.000s 273.219us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 280.942us 1 1 100.00
lc_ctrl_jtag_errors 14.000s 2184.314us 1 1 100.00
lc_ctrl_jtag_access 4.000s 659.711us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.000s 5315.422us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 322.014us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 234.985us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.000s 1209.794us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.000s 1345.405us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.000s 53.240us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 53.924us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 134.219us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.000s 257.441us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 15.144us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 40.000s 6396.956us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 73.531us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 32.994us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 32.994us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 17.749us 1 1 100.00
lc_ctrl_csr_rw 1.000s 16.153us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 415.533us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 57.643us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 17.749us 1 1 100.00
lc_ctrl_csr_rw 1.000s 16.153us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 415.533us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 57.643us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 2.000s 185.122us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 116.015us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 116.015us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.000s 628.404us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 1428.644us 1 1 100.00
lc_ctrl_sec_cm 2.000s 185.122us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 1428.644us 1 1 100.00
lc_ctrl_sec_cm 2.000s 185.122us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 1428.644us 1 1 100.00
lc_ctrl_sec_cm 2.000s 185.122us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 1428.644us 1 1 100.00
lc_ctrl_sec_cm 2.000s 185.122us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 1428.644us 1 1 100.00
lc_ctrl_sec_cm 2.000s 185.122us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 1428.644us 1 1 100.00
lc_ctrl_sec_cm 2.000s 185.122us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 1428.644us 1 1 100.00
lc_ctrl_sec_cm 2.000s 185.122us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.000s 1428.644us 1 1 100.00
lc_ctrl_sec_cm 2.000s 185.122us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.000s 979.723us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.000s 261.205us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3.000s 273.219us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.000s 1732.279us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.000s 1732.279us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.000s 191.491us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 1222.265us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 1222.265us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 14.000s 22832.463us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 109973841349479211058640717663840943437296614085722160779530967546143844353268 699
UVM_INFO @ 22832462518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---