Simulation Results: otbn

 
05/08/2026 19:49:27 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.41 %
  • code
  • 81.81 %
  • assert
  • 89.80 %
  • func
  • 96.61 %
  • block
  • 97.72 %
  • line
  • 97.92 %
  • branch
  • 81.78 %
  • toggle
  • 81.33 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 196.631us 1 1 100.00
single_binary 1 1 100.00
otbn_single 12.000s 66.260us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 53.847us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 14.040us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 7.000s 51.130us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 52.427us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 6.000s 112.818us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 14.040us 1 1 100.00
otbn_csr_aliasing 4.000s 52.427us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 85.000s 5745.843us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 22.000s 654.494us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 44.000s 507.552us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 80.000s 359.412us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 89.000s 273.647us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 26.000s 514.728us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 9.000s 37.604us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 16.286us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 15.000s 43.764us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 7.000s 25.462us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 26.623us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 42.543us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 42.543us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 53.847us 1 1 100.00
otbn_csr_rw 4.000s 14.040us 1 1 100.00
otbn_csr_aliasing 4.000s 52.427us 1 1 100.00
otbn_same_csr_outstanding 4.000s 29.088us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 53.847us 1 1 100.00
otbn_csr_rw 4.000s 14.040us 1 1 100.00
otbn_csr_aliasing 4.000s 52.427us 1 1 100.00
otbn_same_csr_outstanding 4.000s 29.088us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 11.000s 22.874us 1 1 100.00
otbn_dmem_err 8.000s 23.836us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 13.000s 55.790us 1 1 100.00
otbn_controller_ispr_rdata_err 8.000s 154.752us 1 1 100.00
otbn_mac_bignum_acc_err 11.000s 202.526us 1 1 100.00
otbn_urnd_err 5.000s 30.556us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 6.000s 23.185us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 6.000s 64.691us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 39.989us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 319.000s 12096.550us 1 1 100.00
otbn_tl_intg_err 18.000s 225.011us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 23.000s 190.942us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 319.000s 12096.550us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 319.000s 12096.550us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 196.631us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 8.000s 23.836us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 11.000s 22.874us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 18.000s 225.011us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 37.604us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 22.874us 1 1 100.00
otbn_dmem_err 8.000s 23.836us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 16.286us 1 1 100.00
otbn_illegal_mem_acc 6.000s 23.185us 1 1 100.00
otbn_sec_cm 319.000s 12096.550us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 319.000s 12096.550us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 12.000s 66.260us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 22.874us 1 1 100.00
otbn_dmem_err 8.000s 23.836us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 16.286us 1 1 100.00
otbn_illegal_mem_acc 6.000s 23.185us 1 1 100.00
otbn_sec_cm 319.000s 12096.550us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 319.000s 12096.550us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 37.604us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 22.874us 1 1 100.00
otbn_dmem_err 8.000s 23.836us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 16.286us 1 1 100.00
otbn_illegal_mem_acc 6.000s 23.185us 1 1 100.00
otbn_sec_cm 319.000s 12096.550us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 319.000s 12096.550us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 12.000s 66.260us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 8.000s 24.542us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 14.420us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 40.000s 598.157us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 40.000s 598.157us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 55.660us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 319.000s 12096.550us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 319.000s 12096.550us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 16.000s 184.612us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 319.000s 12096.550us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 319.000s 12096.550us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 14.000s 95.495us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 14.000s 95.495us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 6.000s 50.142us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 12.000s 66.260us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 12.000s 66.260us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 12.000s 66.260us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 89.000s 273.647us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 12.000s 66.260us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 12.000s 66.260us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 8.000s 43.002us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 12.000s 66.260us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 319.000s 12096.550us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 69.000s 656.922us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 40.275us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 113638539189373413381609308710227260690956007858026146358109738980909193386541 249
UVM_INFO @ 656921597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---