Simulation Results: otp_ctrl

 
05/08/2026 19:49:27 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.26 %
  • code
  • 72.05 %
  • assert
  • 92.67 %
  • func
  • 55.06 %
  • line
  • 87.47 %
  • branch
  • 84.12 %
  • cond
  • 85.99 %
  • toggle
  • 66.93 %
  • FSM
  • 35.72 %
Validation stages
V1
100.00%
V2
65.00%
V2S
77.78%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.730s 213.144us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 8.060s 3287.671us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.900s 1170.301us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.980s 49.407us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 8.010s 577.025us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.090s 173.117us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.090s 116.465us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.980s 49.407us 1 1 100.00
otp_ctrl_csr_aliasing 4.090s 173.117us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.660s 45.300us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.500s 53.505us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 116.920s 28246.092us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.810s 191.717us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 11.430s 873.773us 0 1 0.00
otp_ctrl_check_fail 12.910s 2650.021us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 4.440s 611.771us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 29.890s 4217.121us 1 1 100.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 13.290s 817.497us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 21.720s 1518.976us 1 1 100.00
otp_ctrl_parallel_lc_esc 5.990s 213.365us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 17.720s 828.573us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 20.720s 19213.298us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 7.020s 4207.252us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 46.310s 6121.465us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.470s 51.318us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.250s 925.835us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 5.380s 307.438us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 5.380s 307.438us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.900s 1170.301us 1 1 100.00
otp_ctrl_csr_rw 1.980s 49.407us 1 1 100.00
otp_ctrl_csr_aliasing 4.090s 173.117us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.890s 1587.076us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.900s 1170.301us 1 1 100.00
otp_ctrl_csr_rw 1.980s 49.407us 1 1 100.00
otp_ctrl_csr_aliasing 4.090s 173.117us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.890s 1587.076us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 261.970s 16322.702us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 261.970s 16322.702us 1 1 100.00
otp_ctrl_tl_intg_err 17.640s 12132.599us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 261.970s 16322.702us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 261.970s 16322.702us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 17.640s 12132.599us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 8.060s 3287.671us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 8.060s 3287.671us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 261.970s 16322.702us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 261.970s 16322.702us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 261.970s 16322.702us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 261.970s 16322.702us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 261.970s 16322.702us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 261.970s 16322.702us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 261.970s 16322.702us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 261.970s 16322.702us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 261.970s 16322.702us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 261.970s 16322.702us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 261.970s 16322.702us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 261.970s 16322.702us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 261.970s 16322.702us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 261.970s 16322.702us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 261.970s 16322.702us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.990s 213.365us 1 1 100.00
otp_ctrl_sec_cm 261.970s 16322.702us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.990s 213.365us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.990s 213.365us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 5.990s 213.365us 1 1 100.00
otp_ctrl_macro_errs 20.720s 19213.298us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.990s 213.365us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.990s 213.365us 1 1 100.00
otp_ctrl_sec_cm 261.970s 16322.702us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.990s 213.365us 1 1 100.00
otp_ctrl_sec_cm 261.970s 16322.702us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.990s 213.365us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.990s 213.365us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 5.990s 213.365us 1 1 100.00
otp_ctrl_macro_errs 20.720s 19213.298us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 5.990s 213.365us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 5.990s 213.365us 1 1 100.00
otp_ctrl_sec_cm 261.970s 16322.702us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.810s 191.717us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 12.910s 2650.021us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 29.890s 4217.121us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 29.890s 4217.121us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 29.890s 4217.121us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 29.890s 4217.121us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 29.890s 4217.121us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 8.060s 3287.671us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 29.890s 4217.121us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 8.060s 3287.671us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 261.970s 16322.702us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 4.440s 611.771us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 8.060s 3287.671us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 8.060s 3287.671us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 20.720s 19213.298us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 56.040s 26185.475us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 39.000s 5334.973us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 3 test runs
otp_ctrl_check_fail 42893089231109016370521262778386400677026845119014466250304976459643908711338 8252
UVM_INFO @ 2650021488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 78883813334954367764492885353038332950791404418783734644307735265974918154762 13187
UVM_INFO @ 19213298237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 89001864026786737564220504150150220408890037248011711584137212906349515326974 8438
UVM_INFO @ 5334972871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 13444737842061715859473369696275072483800965250205275701269053584625494237262 112893
UVM_INFO @ 28246092208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 20098500095432558484912752821963991791588307282072416546416219723024469863942 89
UVM_INFO @ 26185475149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:677) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 1 test run
otp_ctrl_background_chks 84576993312458961331078778591599916524767616150277773367882843037831986140606 9242
UVM_INFO @ 873772628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 1 test run
otp_ctrl_parallel_key_req 114212573671396883149185832029888408710233916139019568736975485416220201942300 9126
UVM_INFO @ 817497221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_test_access 83310286753197594614163519784391018473552969094327061863756243320145933048159 3278
UVM_INFO @ 4207252149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:964) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask * 1 test run
otp_ctrl_stress_all 64092973253463704328099205922503650293933538351552182428094329164001949848408 31848
UVM_INFO @ 6121464523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---