Simulation Results: rom_ctrl/32kb

 
05/08/2026 19:49:27 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.44 %
  • code
  • 83.06 %
  • assert
  • 97.53 %
  • func
  • 90.74 %
  • block
  • 86.67 %
  • line
  • 86.01 %
  • branch
  • 85.35 %
  • toggle
  • 84.69 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.000s 719.626us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.000s 65.734us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.000s 75.718us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 2.000s 84.494us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 59.200us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 2.000s 60.458us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 2.000s 75.718us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 59.200us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 53.645us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 68.690us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 1.000s 9.814us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 3.000s 141.884us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 3.000s 55.815us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 1.000s 68.324us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 183.451us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 183.451us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 65.734us 1 1 100.00
rom_ctrl_csr_rw 2.000s 75.718us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 59.200us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 302.651us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 65.734us 1 1 100.00
rom_ctrl_csr_rw 2.000s 75.718us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 59.200us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 302.651us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 722.562us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 3.000s 181.823us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 97.000s 1514.470us 1 1 100.00
rom_ctrl_tl_intg_err 21.000s 297.195us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 97.000s 1514.470us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 97.000s 1514.470us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 722.562us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 722.562us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 722.562us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 722.562us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 722.562us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 97.000s 1514.470us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 97.000s 1514.470us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.000s 719.626us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.000s 719.626us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.000s 719.626us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 21.000s 297.195us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 722.562us 0 1 0.00
rom_ctrl_kmac_err_chk 3.000s 55.815us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 722.562us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 722.562us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 722.562us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 3.000s 181.823us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 97.000s 1514.470us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 8.000s 3487.801us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 41112732229109387877930333162356413565200782200034877710160907674592466694476 88
UVM_INFO @ 9814314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1049) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] Expected alert (fatal) did not fire in * cycles. 1 test run
rom_ctrl_corrupt_sig_fatal_chk 59359011113930594277954389700279623017458580822387848108988048702819118676456 89
UVM_INFO @ 722562064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 1 test run
rom_ctrl_stress_all_with_rand_reset 13469029686734100780218905669304092069424289439015284330283114300251996053997 93
UVM_INFO @ 3487800582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---