Simulation Results: rom_ctrl/64kb

 
05/08/2026 19:49:27 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.55 %
  • code
  • 83.40 %
  • assert
  • 97.09 %
  • func
  • 97.15 %
  • block
  • 87.04 %
  • line
  • 86.31 %
  • branch
  • 86.36 %
  • toggle
  • 84.74 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.000s 715.674us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.000s 90.975us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.000s 85.099us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 395.566us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 56.091us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.000s 64.783us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.000s 85.099us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 56.091us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 77.646us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.000s 54.996us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.000s 1377.045us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 6.000s 150.632us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 4.000s 64.319us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.000s 75.355us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 1419.985us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.000s 1419.985us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.000s 90.975us 1 1 100.00
rom_ctrl_csr_rw 3.000s 85.099us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 56.091us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 98.016us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.000s 90.975us 1 1 100.00
rom_ctrl_csr_rw 3.000s 85.099us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 56.091us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 98.016us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3.000s 16.235us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 7.000s 250.918us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 97.000s 463.103us 1 1 100.00
rom_ctrl_tl_intg_err 39.000s 412.745us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 97.000s 463.103us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 97.000s 463.103us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3.000s 16.235us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3.000s 16.235us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3.000s 16.235us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3.000s 16.235us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3.000s 16.235us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 97.000s 463.103us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 97.000s 463.103us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.000s 715.674us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.000s 715.674us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.000s 715.674us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 39.000s 412.745us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 3.000s 16.235us 0 1 0.00
rom_ctrl_kmac_err_chk 4.000s 64.319us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3.000s 16.235us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3.000s 16.235us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3.000s 16.235us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 7.000s 250.918us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 97.000s 463.103us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 58.000s 20097.409us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 13859656397553952815857665058336359441951728667836852993386824322826960356088 88
UVM_INFO @ 1377045399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:148) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 1 test run
rom_ctrl_corrupt_sig_fatal_chk 105240136042356425101375945567085837939310774064863682461278843569130058777741 87
UVM_INFO @ 16234925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---