Simulation Results: rstmgr

 
05/08/2026 19:49:27 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.13 %
  • code
  • 99.25 %
  • assert
  • 98.17 %
  • func
  • 96.99 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.64 %
  • toggle
  • 99.43 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.110s 63.472us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.120s 91.962us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.910s 37.739us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.260s 209.535us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.100s 44.024us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.160s 98.090us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.910s 37.739us 1 1 100.00
rstmgr_csr_aliasing 1.100s 44.024us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.570s 96.823us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.930s 39.435us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.960s 80.542us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.800s 677.020us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.800s 677.020us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.800s 677.020us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.800s 677.020us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 7.130s 1029.581us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.040s 40.574us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.760s 46.650us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.760s 46.650us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.120s 91.962us 1 1 100.00
rstmgr_csr_rw 0.910s 37.739us 1 1 100.00
rstmgr_csr_aliasing 1.100s 44.024us 1 1 100.00
rstmgr_same_csr_outstanding 0.890s 41.083us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.120s 91.962us 1 1 100.00
rstmgr_csr_rw 0.910s 37.739us 1 1 100.00
rstmgr_csr_aliasing 1.100s 44.024us 1 1 100.00
rstmgr_same_csr_outstanding 0.890s 41.083us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 29.540s 6831.932us 1 1 100.00
rstmgr_tl_intg_err 2.350s 339.060us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 29.540s 6831.932us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 29.540s 6831.932us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.350s 339.060us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.130s 70.084us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.390s 426.839us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.940s 291.689us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 29.540s 6831.932us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.910s 37.739us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.910s 37.739us 1 1 100.00