Simulation Results: rv_dm/use_dmi_interface

 
05/08/2026 19:49:27 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.53 %
  • code
  • 81.25 %
  • assert
  • 96.59 %
  • func
  • 93.75 %
  • block
  • 92.79 %
  • line
  • 93.31 %
  • branch
  • 80.43 %
  • toggle
  • 72.70 %
  • FSM
  • 78.57 %
Validation stages
V1
96.30%
V2
73.91%
V2S
85.71%
V3
100.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 33.000s 3593.434us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 34.000s 255.178us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 33.000s 151.120us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 62.000s 23547.481us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 31.000s 209.617us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 32.000s 1815.693us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 33.000s 5523.908us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 30.000s 67.121us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 39.000s 28321.940us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 31.000s 557.277us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 31.000s 597.642us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 31.000s 431.322us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 31.000s 434.238us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 31.000s 267.622us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 31.000s 737.009us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 31.000s 419.599us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 31.000s 267.195us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 31.000s 557.277us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 31.000s 458.282us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 33.000s 1219.701us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 31.000s 431.322us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 31.000s 175.970us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 34.000s 449.987us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 32.000s 112.294us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 54.000s 4683.090us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 47.000s 14621.957us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_dm_csr_mem_rw_with_rand_reset 35.000s 503.582us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 47.000s 14621.957us 1 1 100.00
rv_dm_csr_rw 32.000s 112.294us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 29.000s 147.812us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 30.000s 152.495us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 33.000s 3593.434us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 31.000s 455.133us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 30.000s 184.114us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 34.000s 188.708us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 37.000s 510.110us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 42.000s 15992.988us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 30.000s 457.687us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 31.000s 201.790us 0 1 0.00
sba_autoincrement 1 1 100.00
rv_dm_autoincr_sba_tl_access 32.000s 3724.910us 1 1 100.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 29.000s 92.637us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 33.000s 1256.076us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 30.000s 462.065us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 29.000s 114.430us 0 1 0.00
tap_ctrl_transitions 2 2 100.00
rv_dm_tap_fsm 46.000s 9341.465us 1 1 100.00
rv_dm_tap_fsm_rand_reset 41.000s 700.642us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 30.000s 357.143us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 31.000s 762.429us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 32.000s 153.420us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_dm_tl_errors 37.000s 362.688us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_dm_tl_errors 37.000s 362.688us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 47.000s 14621.957us 1 1 100.00
rv_dm_csr_hw_reset 34.000s 449.987us 1 1 100.00
rv_dm_csr_rw 32.000s 112.294us 1 1 100.00
rv_dm_same_csr_outstanding 33.000s 346.849us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 47.000s 14621.957us 1 1 100.00
rv_dm_csr_hw_reset 34.000s 449.987us 1 1 100.00
rv_dm_csr_rw 32.000s 112.294us 1 1 100.00
rv_dm_same_csr_outstanding 33.000s 346.849us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_sec_cm 35.000s 764.027us 1 1 100.00
rv_dm_tl_intg_err 44.000s 8580.238us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 44.000s 8580.238us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 33.000s 1256.076us 1 1 100.00
rv_dm_debug_disabled 31.000s 154.753us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 33.000s 1256.076us 1 1 100.00
rv_dm_debug_disabled 31.000s 154.753us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 33.000s 3593.434us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 0 1 0.00
rv_dm_buffered_enable 30.000s 96.068us 0 1 0.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 34.000s 61.795us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 34.000s 61.795us 1 1 100.00
sec_cm_exec_ctrl_mubi 0 1 0.00
rv_dm_buffered_enable 30.000s 96.068us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rv_dm_stress_all_with_rand_reset 53.000s 1471.864us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 529.000s 300000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp 2 test runs
rv_dm_delayed_resp_sba_tl_access 32909218843469902787201146057804899060512304735728672826638388065293007016770 107
UVM_INFO @ 457686727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 65012524271464656969860371247398048656786902820014706587789717092961115323238 107
UVM_INFO @ 201789614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) 2 test runs
rv_dm_jtag_dmi_debug_disabled 103273875885180937564739610524215862748244828710097099980094627183729147258744 87
UVM_INFO @ 92637272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 79552846703091859196969471161969676569026294065536798575611823856312186750896 91
UVM_INFO @ 762428882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared: 1 test run
rv_dm_sba_tl_access 36586026116212394102701026715661056663515551450931903987685933348262721994225 87
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23823
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == *'b* (* [*] vs * [*]) 1 test run
rv_dm_mem_tl_access_resuming 15072911125488845008461128200316590940441737746996042350333311809138028387153 87
UVM_INFO @ 434238323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [*] vs * [*]) 1 test run
rv_dm_hart_unavail 23985370824063962438798899111683577289171263730134364835708866744432609034786 87
UVM_INFO @ 114430228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [*] vs * [*]) 1 test run
rv_dm_buffered_enable 77783981152889787645025964165562292025482157123308831534508529138463720492805 92
UVM_INFO @ 96068102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
rv_dm_scanmode 68368973950521396274373245312969593922891336285464806665159069959506185612207 87
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---