Simulation Results: spi_device/1r1w

 
05/08/2026 19:49:27 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.23 %
  • code
  • 89.53 %
  • assert
  • 95.40 %
  • func
  • 70.76 %
  • block
  • 98.36 %
  • line
  • 98.76 %
  • branch
  • 97.03 %
  • toggle
  • 72.75 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 137.000s 28100.881us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.000s 133.256us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.000s 144.714us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 32.000s 1943.675us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 22.000s 1156.828us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 4.000s 157.185us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.000s 144.714us 1 1 100.00
spi_device_csr_aliasing 22.000s 1156.828us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.000s 32.218us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 3.000s 82.027us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 44.425us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 1.000s 12.871us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 2.000s 3.678us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.000s 112.623us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.000s 112.623us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 8.000s 3323.880us 1 1 100.00
spi_device_tpm_sts_read 2.000s 135.212us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 46.000s 40982.979us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 17.000s 2751.891us 1 1 100.00
spi_device_flash_all 11.000s 1893.562us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 8.000s 500.917us 1 1 100.00
spi_device_flash_all 11.000s 1893.562us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 8.000s 500.917us 1 1 100.00
spi_device_flash_all 11.000s 1893.562us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 11.000s 1893.562us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.000s 73.861us 1 1 100.00
spi_device_flash_all 11.000s 1893.562us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.000s 73.861us 1 1 100.00
spi_device_flash_all 11.000s 1893.562us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.000s 73.861us 1 1 100.00
spi_device_flash_all 11.000s 1893.562us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.000s 73.861us 1 1 100.00
spi_device_flash_all 11.000s 1893.562us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.000s 73.861us 1 1 100.00
spi_device_flash_all 11.000s 1893.562us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 26.000s 3974.295us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 16.000s 936.040us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 16.000s 936.040us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 16.000s 936.040us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 53.000s 76544.341us 1 1 100.00
spi_device_read_buffer_direct 6.000s 207.827us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 16.000s 936.040us 1 1 100.00
spi_device_flash_all 11.000s 1893.562us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 11.000s 1893.562us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 11.000s 1893.562us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 4.000s 135.102us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 4.000s 135.102us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 94.000s 40795.501us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 137.000s 28100.881us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 330.000s 32832.231us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 109.000s 5120.501us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 1.000s 10.963us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.000s 77.087us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.000s 165.264us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.000s 165.264us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.000s 133.256us 1 1 100.00
spi_device_csr_rw 2.000s 144.714us 1 1 100.00
spi_device_csr_aliasing 22.000s 1156.828us 1 1 100.00
spi_device_same_csr_outstanding 2.000s 53.627us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.000s 133.256us 1 1 100.00
spi_device_csr_rw 2.000s 144.714us 1 1 100.00
spi_device_csr_aliasing 22.000s 1156.828us 1 1 100.00
spi_device_same_csr_outstanding 2.000s 53.627us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 3.000s 154.518us 1 1 100.00
spi_device_tl_intg_err 8.000s 711.251us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 8.000s 711.251us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 89868225218246234778415710234475306705020993430162127064416738918527135640919 87
UVM_ERROR @ 10416896 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[918] not found within the scope .
UVM_ERROR @ 10416896 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[918] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 30098458500100080513416191485717989722238236801739396350926152743263305558934 85
UVM_ERROR @ 1256478 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x72 [1110010] vs 0x0 [0])
UVM_ERROR @ 1302478 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x11c [100011100] vs 0x0 [0])
UVM_ERROR @ 1376478 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x49 [1001001] vs 0x0 [0])
UVM_ERROR @ 1470478 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2ca [1011001010] vs 0x0 [0])