Simulation Results: spi_host

 
05/08/2026 19:49:27 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.56 %
  • code
  • 91.16 %
  • assert
  • 95.27 %
  • func
  • 88.24 %
  • block
  • 96.78 %
  • line
  • 98.54 %
  • branch
  • 93.05 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
90.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 21.000s 869.868us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 53.423us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 37.946us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 568.656us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 17.544us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 130.565us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 37.946us 1 1 100.00
spi_host_csr_aliasing 1.000s 17.544us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 70.911us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 201.796us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 305.763us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 78.067us 1 1 100.00
spi_host_error_cmd 2.000s 136.361us 1 1 100.00
spi_host_event 25.000s 1183.262us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 6.000s 1884.838us 1 1 100.00
speed 1 1 100.00
spi_host_speed 6.000s 1884.838us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 6.000s 1884.838us 1 1 100.00
upper_range_clkdiv 0 1 0.00
spi_host_upper_range_clkdiv 526.000s 137695.397us 0 1 0.00
sw_reset 1 1 100.00
spi_host_sw_reset 1.000s 93.746us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 63.973us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 6.000s 1884.838us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 6.000s 1884.838us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 21.000s 869.868us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 21.000s 869.868us 1 1 100.00
stress_all 0 1 0.00
spi_host_stress_all 1297.000s 1000000.000us 0 1 0.00
spien 1 1 100.00
spi_host_spien 12.000s 3781.751us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 72.000s 8018.413us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 36.303us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 78.067us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 58.834us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 15.197us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 1.000s 87.810us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 1.000s 87.810us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 53.423us 1 1 100.00
spi_host_csr_rw 1.000s 37.946us 1 1 100.00
spi_host_csr_aliasing 1.000s 17.544us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 37.227us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 53.423us 1 1 100.00
spi_host_csr_rw 1.000s 37.946us 1 1 100.00
spi_host_csr_aliasing 1.000s 17.544us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 37.227us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 179.035us 1 1 100.00
spi_host_sec_cm 1.000s 45.528us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 179.035us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* 1 test run
spi_host_upper_range_clkdiv 71260315961222023770562381405177709258004430563541564740733433873790236270596 177
UVM_INFO @ 137695396837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
spi_host_stress_all 38178481156416017603004197063942980046645290287947470592517195977287378172349 324
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---