Simulation Results: sram_ctrl/main

 
05/08/2026 19:49:27 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.47 %
  • code
  • 94.71 %
  • assert
  • 97.69 %
  • func
  • 94.00 %
  • block
  • 94.74 %
  • line
  • 95.27 %
  • branch
  • 91.72 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 6.000s 693.111us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 16.121us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 28.786us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 110.333us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 22.411us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 698.246us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 28.786us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 22.411us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 92.000s 3084.936us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 98.000s 92798.317us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 20.000s 11801.563us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 115.000s 3358.400us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 120.000s 20321.065us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 22.000s 7289.621us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 14.000s 16404.299us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 28.000s 6282.892us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 1360.642us 1 1 100.00
sram_ctrl_partial_access_b2b 203.000s 16071.533us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 3.000s 685.653us 1 1 100.00
sram_ctrl_throughput_w_partial_write 3.000s 710.820us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 1432.363us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 11.000s 980.412us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 1354.572us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 412.000s 25117.945us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 31.351us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 119.657us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 119.657us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 16.121us 1 1 100.00
sram_ctrl_csr_rw 1.000s 28.786us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 22.411us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 20.465us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 16.121us 1 1 100.00
sram_ctrl_csr_rw 1.000s 28.786us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 22.411us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 20.465us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 12.000s 3882.220us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 1413.345us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 233.203us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 1413.345us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 233.203us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 980.412us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 980.412us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 28.786us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 28.000s 6282.892us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 28.000s 6282.892us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 28.000s 6282.892us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 14.000s 16404.299us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 2024.619us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 12.000s 3882.220us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 7.000s 3899.213us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 693.111us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 693.111us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 28.000s 6282.892us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 1413.345us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 14.000s 16404.299us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 1413.345us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1413.345us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 6.000s 693.111us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1413.345us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 12.000s 419.654us 1 1 100.00