Simulation Results: sram_ctrl/ret

 
05/08/2026 19:49:27 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.73 %
  • code
  • 81.51 %
  • assert
  • 97.67 %
  • func
  • 96.00 %
  • block
  • 92.73 %
  • line
  • 93.63 %
  • branch
  • 87.60 %
  • toggle
  • 78.13 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 233.391us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 145.166us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 67.961us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.000s 66.381us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 42.598us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 75.232us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 67.961us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 42.598us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 8.000s 204.587us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 312.930us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 10.000s 841.290us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 123.000s 2695.658us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 5.000s 258.793us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 3.000s 219.334us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.000s 767.128us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 10.000s 2019.417us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.000s 41.417us 1 1 100.00
sram_ctrl_partial_access_b2b 186.000s 14715.923us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 1.000s 45.341us 1 1 100.00
sram_ctrl_throughput_w_partial_write 1.000s 124.856us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 77.160us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 8.000s 1276.856us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 75.274us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 24.000s 1112.118us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 34.827us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 104.300us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 104.300us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 145.166us 1 1 100.00
sram_ctrl_csr_rw 1.000s 67.961us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 42.598us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 31.432us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 145.166us 1 1 100.00
sram_ctrl_csr_rw 1.000s 67.961us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 42.598us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 31.432us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 262.496us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 588.433us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 274.592us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 588.433us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 274.592us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 1276.856us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 1276.856us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 67.961us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 10.000s 2019.417us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 10.000s 2019.417us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 10.000s 2019.417us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.000s 767.128us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 43.944us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 262.496us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 36.074us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 233.391us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 233.391us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 10.000s 2019.417us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 588.433us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.000s 767.128us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 588.433us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 588.433us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 233.391us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 588.433us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 92.000s 2945.644us 1 1 100.00