Simulation Results: uart

 
05/08/2026 19:49:27 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.83 %
  • code
  • 92.53 %
  • assert
  • 98.27 %
  • func
  • 90.69 %
  • block
  • 98.83 %
  • line
  • 99.24 %
  • branch
  • 97.79 %
  • toggle
  • 73.08 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.000s 125.062us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 2.000s 77.315us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 32.862us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.000s 171.699us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 20.176us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 81.728us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 32.862us 1 1 100.00
uart_csr_aliasing 1.000s 20.176us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 80.000s 139870.384us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.000s 125.062us 1 1 100.00
uart_tx_rx 80.000s 139870.384us 1 1 100.00
parity_error 2 2 100.00
uart_intr 51.000s 45369.772us 1 1 100.00
uart_rx_parity_err 45.000s 152370.675us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 80.000s 139870.384us 1 1 100.00
uart_intr 51.000s 45369.772us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 206.000s 136769.185us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 35.000s 104153.516us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 11.000s 8408.481us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 51.000s 45369.772us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 51.000s 45369.772us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 51.000s 45369.772us 1 1 100.00
perf 1 1 100.00
uart_perf 95.000s 9408.805us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 11.000s 7465.234us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 11.000s 7465.234us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 15.000s 72416.867us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 7.000s 4176.815us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 3.000s 1357.020us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 8.000s 5289.438us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 229.000s 292365.300us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 31.000s 111895.181us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 2.000s 26.406us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 44.898us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.000s 42.513us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.000s 42.513us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 2.000s 77.315us 1 1 100.00
uart_csr_rw 1.000s 32.862us 1 1 100.00
uart_csr_aliasing 1.000s 20.176us 1 1 100.00
uart_same_csr_outstanding 1.000s 36.254us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 2.000s 77.315us 1 1 100.00
uart_csr_rw 1.000s 32.862us 1 1 100.00
uart_csr_aliasing 1.000s 20.176us 1 1 100.00
uart_same_csr_outstanding 1.000s 36.254us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 41.057us 1 1 100.00
uart_tl_intg_err 2.000s 73.768us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 2.000s 73.768us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 38.000s 15444.918us 1 1 100.00