Simulation Results: ac_range_check

 
06/08/2026 19:53:31 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.94 %
  • code
  • 93.09 %
  • assert
  • 97.75 %
  • func
  • 57.98 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 81.09 %
Validation stages
V1
100.00%
V2
90.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 20.000s 495.858us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 32.000s 5239.128us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 43.347us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 78.223us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 32.000s 10969.887us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 18.000s 2417.984us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 44.548us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 78.223us 1 1 100.00
ac_range_check_csr_aliasing 18.000s 2417.984us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 551.019us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 26.000s 1400.249us 1 1 100.00
stress_all 0 1 0.00
ac_range_check_stress_all 42.000s 939.962us 0 1 0.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 64.578us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 2.000s 40.585us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 2.000s 352.481us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 2.000s 352.481us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 43.347us 1 1 100.00
ac_range_check_csr_rw 2.000s 78.223us 1 1 100.00
ac_range_check_csr_aliasing 18.000s 2417.984us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 211.920us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 43.347us 1 1 100.00
ac_range_check_csr_rw 2.000s 78.223us 1 1 100.00
ac_range_check_csr_aliasing 18.000s 2417.984us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 211.920us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 942.666us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 942.666us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 942.666us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 12.000s 942.666us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 85.000s 10681.632us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 14.384us 1 1 100.00
ac_range_check_tl_intg_err 7.000s 341.914us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 174.000s 513.188us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 27.000s 1538.869us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state 1 test run
ac_range_check_stress_all 101188013042929240271946074277183473160241435934483468993832811905593127123163 8700
UVM_INFO @ 939962135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---