Simulation Results: aes/gcm_unmasked

 
06/08/2026 19:53:31 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.60 %
  • code
  • 91.04 %
  • assert
  • 97.94 %
  • func
  • 64.81 %
  • block
  • 91.46 %
  • line
  • 92.86 %
  • branch
  • 84.67 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
88.24%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 115.026us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 562.994us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 138.901us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 54.883us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 470.190us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 4.000s 869.188us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 62.145us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 54.883us 1 1 100.00
aes_csr_aliasing 4.000s 869.188us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 562.994us 1 1 100.00
aes_config_error 2.000s 326.831us 1 1 100.00
aes_stress 2.000s 93.848us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 562.994us 1 1 100.00
aes_config_error 2.000s 326.831us 1 1 100.00
aes_stress 2.000s 93.848us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 93.848us 1 1 100.00
aes_b2b 6.000s 141.613us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 93.848us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 3.000s 562.994us 1 1 100.00
aes_config_error 2.000s 326.831us 1 1 100.00
aes_stress 2.000s 93.848us 1 1 100.00
aes_alert_reset 2425.000s 200000.000us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 85.944us 1 1 100.00
aes_config_error 2.000s 326.831us 1 1 100.00
aes_alert_reset 2425.000s 200000.000us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 64.957us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 1307.952us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 2425.000s 200000.000us 0 1 0.00
stress 1 1 100.00
aes_stress 2.000s 93.848us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 93.848us 1 1 100.00
aes_sideload 2.000s 111.688us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 115.492us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 4.000s 504.787us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 71.979us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 1.000s 58.544us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 1.000s 58.544us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 138.901us 1 1 100.00
aes_csr_rw 2.000s 54.883us 1 1 100.00
aes_csr_aliasing 4.000s 869.188us 1 1 100.00
aes_same_csr_outstanding 2.000s 102.766us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 138.901us 1 1 100.00
aes_csr_rw 2.000s 54.883us 1 1 100.00
aes_csr_aliasing 4.000s 869.188us 1 1 100.00
aes_same_csr_outstanding 2.000s 102.766us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 103.753us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 54.940us 1 1 100.00
aes_cipher_fi 2.000s 58.601us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 455.829us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 455.829us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 455.829us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 455.829us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 267.273us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 685.250us 1 1 100.00
aes_tl_intg_err 2.000s 343.851us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 343.851us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 2425.000s 200000.000us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 455.829us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 455.829us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 3.000s 562.994us 1 1 100.00
aes_stress 2.000s 93.848us 1 1 100.00
aes_alert_reset 2425.000s 200000.000us 0 1 0.00
aes_core_fi 1.000s 71.490us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 326.831us 1 1 100.00
aes_stress 2.000s 93.848us 1 1 100.00
aes_core_fi 1.000s 71.490us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 455.829us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 54.169us 1 1 100.00
aes_stress 2.000s 93.848us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 93.848us 1 1 100.00
aes_sideload 2.000s 111.688us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 54.169us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 54.169us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 54.169us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 54.169us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 54.169us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 93.848us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 93.848us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 54.940us 1 1 100.00
aes_cipher_fi 2.000s 58.601us 1 1 100.00
aes_ctr_fi 2.000s 55.285us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 54.940us 1 1 100.00
aes_cipher_fi 2.000s 58.601us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 58.601us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 54.940us 1 1 100.00
aes_ctr_fi 2.000s 55.285us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 54.940us 1 1 100.00
aes_cipher_fi 2.000s 58.601us 1 1 100.00
aes_ctr_fi 2.000s 55.285us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 2425.000s 200000.000us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 54.940us 1 1 100.00
aes_cipher_fi 2.000s 58.601us 1 1 100.00
aes_ctr_fi 2.000s 55.285us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 54.940us 1 1 100.00
aes_cipher_fi 2.000s 58.601us 1 1 100.00
aes_ctr_fi 2.000s 55.285us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 54.940us 1 1 100.00
aes_ctr_fi 2.000s 55.285us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 2.000s 54.940us 1 1 100.00
aes_cipher_fi 2.000s 58.601us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 1.000s 1.762us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
aes_alert_reset 20088022979994648736769544983060464725049458748596162587476656389460391589483 32664458
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
aes_fi 75392270477500542460825211436526748901077098498507124888596028147487383338379 None
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all 13651571147154215343886666013017367374748322392287539434013218733162237144724 21906
UVM_INFO @ 504786633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 31645139084243009317177112136495230541409738623387162672996644631936098198764 138
UVM_INFO @ 1762358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---