Simulation Results: clkmgr

 
06/08/2026 19:53:31 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 77.33 %
  • code
  • 69.83 %
  • assert
  • 90.08 %
  • func
  • 72.09 %
  • line
  • 82.37 %
  • branch
  • 87.42 %
  • cond
  • 79.54 %
  • toggle
  • 99.81 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
61.54%
V2S
50.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.900s 25.361us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.800s 21.815us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.890s 26.299us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 0.650s 3.269us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.820s 10.630us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 1.050s 40.209us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.890s 26.299us 1 1 100.00
clkmgr_csr_aliasing 0.820s 10.630us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.820s 153.047us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.380s 94.761us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.110s 48.902us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.900s 25.361us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.670s 5.092us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.710s 6.829us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.670s 5.092us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.810s 25.016us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.880s 23.862us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 4.540s 379.759us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 4.540s 379.759us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 0.800s 21.815us 1 1 100.00
clkmgr_csr_rw 0.890s 26.299us 1 1 100.00
clkmgr_csr_aliasing 0.820s 10.630us 0 1 0.00
clkmgr_same_csr_outstanding 1.230s 55.089us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 0.800s 21.815us 1 1 100.00
clkmgr_csr_rw 0.890s 26.299us 1 1 100.00
clkmgr_csr_aliasing 0.820s 10.630us 0 1 0.00
clkmgr_same_csr_outstanding 1.230s 55.089us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 4.970s 511.520us 1 1 100.00
clkmgr_tl_intg_err 0.680s 2.358us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.040s 37.418us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.040s 37.418us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.040s 37.418us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.040s 37.418us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.950s 28.435us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.680s 2.358us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.670s 5.092us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.710s 6.829us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.040s 37.418us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.120s 43.561us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.890s 26.299us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 4.970s 511.520us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.890s 26.299us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.890s 26.299us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 4.970s 511.520us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.740s 3.294us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 43.280s 4144.751us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 3 test runs
clkmgr_frequency_timeout 17579317262480234310917227845299540554506638384752561959197076283266866954411 78
UVM_INFO @ 6828765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 62478479204037656822128329876655464434775433132781754427531498565370230222752 100
UVM_INFO @ 4144750977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 117866316898352031375865978403399456845841672923101672515179812391945662965 78
UVM_INFO @ 25016252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 3 test runs
clkmgr_shadow_reg_errors_with_csr_rw 33952206894600969119206229285917443565591478018952346331009058166737263113861 75
UVM_INFO @ 28434923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 96422790572954800415583661006842257876875580878956994113436900587641954266856 82
UVM_INFO @ 2358344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 7008267024217721489815018954351170815145979687568973769814995639397439461508 82
UVM_INFO @ 40209153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 1 test run
clkmgr_frequency 103740955255484906598406442454956120554471869489489311771744218865669985919640 76
UVM_INFO @ 5091895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed 1 test run
clkmgr_regwen 57696570346132514006793008315033369895450889769300249586355714998162094236398 74
UVM_INFO @ 3293636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 10021264928791383872160741297605774392974374360645365803489499708186240062357 75
UVM_INFO @ 3269423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 1 test run
clkmgr_csr_aliasing 85803000011572032742830248722408047927538986018988487788412606506119256254014 75
UVM_INFO @ 10630018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 12906988369809803595053623539383739412210039718833200332969129703889488409998 76
UVM_INFO @ 55088931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---