Simulation Results: dma

 
06/08/2026 19:53:31 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.81 %
  • code
  • 90.41 %
  • assert
  • 96.50 %
  • func
  • 61.53 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 77.37 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 605.266us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 661.962us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 4.000s 588.518us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 25.302us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 63.891us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 6.000s 229.078us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 5.000s 1020.672us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 30.767us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 63.891us 1 1 100.00
dma_csr_aliasing 5.000s 1020.672us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 67.000s 5237.676us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 267.000s 180177.686us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 1431.000s 124945.616us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 1431.000s 124945.616us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 267.000s 180177.686us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 231.000s 40932.348us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 1431.000s 124945.616us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 8.000s 728.954us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 155.000s 252754.452us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 20.719us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 24.503us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 34.333us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 34.333us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 25.302us 1 1 100.00
dma_csr_rw 1.000s 63.891us 1 1 100.00
dma_csr_aliasing 5.000s 1020.672us 1 1 100.00
dma_same_csr_outstanding 2.000s 42.127us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 25.302us 1 1 100.00
dma_csr_rw 1.000s 63.891us 1 1 100.00
dma_csr_aliasing 5.000s 1020.672us 1 1 100.00
dma_same_csr_outstanding 2.000s 42.127us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 8.000s 938.585us 1 1 100.00
dma_generic_stress 231.000s 40932.348us 1 1 100.00
dma_handshake_stress 1431.000s 124945.616us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 6.000s 1376.630us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 2.000s 226.464us 1 1 100.00
dma_sec_cm 2.000s 13.530us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 90.000s 21594.093us 1 1 100.00
dma_longer_transfer 3.000s 167.797us 1 1 100.00
dma_stress_all_with_rand_reset 14.000s 1813.467us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 49341602785716774947816796153742057032303013525331015019504377243075305685769 121
UVM_INFO @ 1813467005ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---