Simulation Results: edn/edn0

 
06/08/2026 19:53:31 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 78.22 %
  • code
  • 89.19 %
  • assert
  • 96.24 %
  • func
  • 49.23 %
  • block
  • 95.60 %
  • line
  • 97.95 %
  • branch
  • 90.33 %
  • toggle
  • 75.44 %
  • FSM
  • 93.02 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 18.730us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 45.858us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 18.010us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.000s 323.193us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.000s 18.730us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 29.511us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 18.010us 1 1 100.00
edn_csr_aliasing 1.000s 18.730us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.000s 96.095us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.000s 96.095us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.000s 96.095us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 28.617us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 95.227us 1 1 100.00
errs 1 1 100.00
edn_err 1.000s 29.980us 1 1 100.00
disable 2 2 100.00
edn_disable 2.000s 38.293us 1 1 100.00
edn_disable_auto_req_mode 2.000s 45.815us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 5.000s 552.646us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 2.000s 15.979us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.000s 66.083us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.000s 584.042us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.000s 584.042us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 2.000s 45.858us 1 1 100.00
edn_csr_rw 2.000s 18.010us 1 1 100.00
edn_csr_aliasing 1.000s 18.730us 1 1 100.00
edn_same_csr_outstanding 1.000s 69.724us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 2.000s 45.858us 1 1 100.00
edn_csr_rw 2.000s 18.010us 1 1 100.00
edn_csr_aliasing 1.000s 18.730us 1 1 100.00
edn_same_csr_outstanding 1.000s 69.724us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.000s 1175.808us 1 1 100.00
edn_tl_intg_err 2.000s 67.011us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.000s 18.614us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 95.227us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.000s 1175.808us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.000s 1175.808us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.000s 1175.808us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.000s 1175.808us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 95.227us 1 1 100.00
edn_sec_cm 5.000s 1175.808us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 95.227us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.000s 67.011us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 36.000s 1767.211us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
edn_stress_all_with_rand_reset 16382981860783552467823254186727881533474007724661930624704331259565014944447 221
UVM_INFO @ 1767211214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---