Simulation Results: edn/edn1

 
06/08/2026 19:53:31 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.36 %
  • code
  • 81.18 %
  • assert
  • 98.70 %
  • func
  • 79.20 %
  • line
  • 97.72 %
  • branch
  • 91.99 %
  • cond
  • 89.15 %
  • toggle
  • 86.14 %
  • FSM
  • 40.91 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.010s 45.582us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.740s 17.201us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.930s 13.346us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.890s 2760.659us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.430s 147.417us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.240s 39.524us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.930s 13.346us 1 1 100.00
edn_csr_aliasing 1.430s 147.417us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.920s 92.844us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.920s 92.844us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.920s 92.844us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.280s 21.489us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.920s 43.409us 1 1 100.00
errs 1 1 100.00
edn_err 1.000s 26.982us 1 1 100.00
disable 2 2 100.00
edn_disable 0.790s 36.660us 1 1 100.00
edn_disable_auto_req_mode 1.050s 38.701us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 0.950s 125.402us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.880s 11.998us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.720s 63.055us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.210s 334.488us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.210s 334.488us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.740s 17.201us 1 1 100.00
edn_csr_rw 0.930s 13.346us 1 1 100.00
edn_csr_aliasing 1.430s 147.417us 1 1 100.00
edn_same_csr_outstanding 1.230s 89.523us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.740s 17.201us 1 1 100.00
edn_csr_rw 0.930s 13.346us 1 1 100.00
edn_csr_aliasing 1.430s 147.417us 1 1 100.00
edn_same_csr_outstanding 1.230s 89.523us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.410s 393.595us 1 1 100.00
edn_tl_intg_err 1.840s 98.695us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.860s 35.084us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.920s 43.409us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.410s 393.595us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.410s 393.595us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.410s 393.595us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.410s 393.595us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.920s 43.409us 1 1 100.00
edn_sec_cm 2.410s 393.595us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.920s 43.409us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.840s 98.695us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 38.550s 4512.950us 1 1 100.00