Simulation Results: entropy_src/rng_16bits

 
06/08/2026 19:53:31 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 69.05 %
  • code
  • 82.88 %
  • assert
  • 73.36 %
  • func
  • 50.91 %
  • block
  • 94.19 %
  • line
  • 97.86 %
  • branch
  • 86.25 %
  • toggle
  • 52.62 %
  • FSM
  • 94.79 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 123.066us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 30.862us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 32.256us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 14.000s 828.853us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 4.000s 210.103us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 2.000s 12.435us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 32.256us 1 1 100.00
entropy_src_csr_aliasing 4.000s 210.103us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 123.066us 1 1 100.00
entropy_src_rng 35.000s 13669.754us 1 1 100.00
entropy_src_fw_ov 101.000s 14156.417us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 101.000s 14156.417us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 35.000s 13669.754us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 219.000s 13022.821us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 35.000s 13669.754us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 35.000s 13669.754us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 35.000s 13669.754us 1 1 100.00
entropy_src_intr 2.000s 26.929us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 35.000s 13669.754us 1 1 100.00
entropy_src_functional_alerts 6.000s 171.013us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 53.000s 15220.594us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 31.548us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 4.000s 478.064us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 19.023us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 60.749us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 2.000s 26.783us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 2.000s 26.783us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 30.862us 1 1 100.00
entropy_src_csr_rw 2.000s 32.256us 1 1 100.00
entropy_src_csr_aliasing 4.000s 210.103us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 167.958us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 30.862us 1 1 100.00
entropy_src_csr_rw 2.000s 32.256us 1 1 100.00
entropy_src_csr_aliasing 4.000s 210.103us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 167.958us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 102.515us 1 1 100.00
entropy_src_tl_intg_err 4.000s 1074.060us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 35.000s 13669.754us 1 1 100.00
entropy_src_cfg_regwen 2.000s 64.442us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 35.000s 13669.754us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 35.000s 13669.754us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 35.000s 13669.754us 1 1 100.00
entropy_src_fw_ov 101.000s 14156.417us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 31.548us 1 1 100.00
entropy_src_sec_cm 2.000s 102.515us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 31.548us 1 1 100.00
entropy_src_sec_cm 2.000s 102.515us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 35.000s 13669.754us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 31.548us 1 1 100.00
entropy_src_sec_cm 2.000s 102.515us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 31.548us 1 1 100.00
entropy_src_sec_cm 2.000s 102.515us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 31.548us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 6.000s 171.013us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 4.000s 1074.060us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 293.000s 14012.917us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 11.000s 399.094us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (entropy_src_base_vseq.sv:134) virtual_sequencer [write] Writing '* to intr_state failed 1 test run
entropy_src_stress_all_with_rand_reset 2065310554080397386823295804241356386593161683497564375312302103336190939663 944
UVM_INFO @ 399094165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror markov_lo_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 21162071507044077083109328484540715818390566469102604843553382785995234389504 113
UVM_INFO @ 12435483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---