Simulation Results: hmac

 
06/08/2026 19:53:31 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 73.71 %
  • code
  • 95.25 %
  • assert
  • 96.96 %
  • func
  • 28.92 %
  • block
  • 97.18 %
  • line
  • 97.99 %
  • branch
  • 92.93 %
  • toggle
  • 96.96 %
  • FSM
  • 93.10 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 10.000s 1035.260us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 173.174us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 34.184us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 12.000s 1184.954us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.000s 695.501us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.000s 18.703us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 34.184us 1 1 100.00
hmac_csr_aliasing 3.000s 695.501us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 25.000s 1240.703us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 4.000s 224.167us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 12.000s 464.154us 1 1 100.00
hmac_test_sha384_vectors 451.000s 22561.763us 1 1 100.00
hmac_test_sha512_vectors 411.000s 48022.360us 1 1 100.00
hmac_test_hmac256_vectors 13.000s 436.006us 1 1 100.00
hmac_test_hmac384_vectors 10.000s 4687.697us 1 1 100.00
hmac_test_hmac512_vectors 16.000s 411.450us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 17.000s 12117.843us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 22.000s 3040.797us 1 1 100.00
error 1 1 100.00
hmac_error 42.000s 10045.586us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 53.000s 21650.257us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 10.000s 1035.260us 1 1 100.00
hmac_long_msg 25.000s 1240.703us 1 1 100.00
hmac_back_pressure 4.000s 224.167us 1 1 100.00
hmac_datapath_stress 22.000s 3040.797us 1 1 100.00
hmac_burst_wr 17.000s 12117.843us 1 1 100.00
hmac_stress_all 401.000s 12947.132us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 10.000s 1035.260us 1 1 100.00
hmac_long_msg 25.000s 1240.703us 1 1 100.00
hmac_back_pressure 4.000s 224.167us 1 1 100.00
hmac_datapath_stress 22.000s 3040.797us 1 1 100.00
hmac_wipe_secret 53.000s 21650.257us 1 1 100.00
hmac_test_sha256_vectors 12.000s 464.154us 1 1 100.00
hmac_test_sha384_vectors 451.000s 22561.763us 1 1 100.00
hmac_test_sha512_vectors 411.000s 48022.360us 1 1 100.00
hmac_test_hmac256_vectors 13.000s 436.006us 1 1 100.00
hmac_test_hmac384_vectors 10.000s 4687.697us 1 1 100.00
hmac_test_hmac512_vectors 16.000s 411.450us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 10.000s 1035.260us 1 1 100.00
hmac_long_msg 25.000s 1240.703us 1 1 100.00
hmac_back_pressure 4.000s 224.167us 1 1 100.00
hmac_datapath_stress 22.000s 3040.797us 1 1 100.00
hmac_burst_wr 17.000s 12117.843us 1 1 100.00
hmac_error 42.000s 10045.586us 1 1 100.00
hmac_wipe_secret 53.000s 21650.257us 1 1 100.00
hmac_test_sha256_vectors 12.000s 464.154us 1 1 100.00
hmac_test_sha384_vectors 451.000s 22561.763us 1 1 100.00
hmac_test_sha512_vectors 411.000s 48022.360us 1 1 100.00
hmac_test_hmac256_vectors 13.000s 436.006us 1 1 100.00
hmac_test_hmac384_vectors 10.000s 4687.697us 1 1 100.00
hmac_test_hmac512_vectors 16.000s 411.450us 1 1 100.00
hmac_stress_all 401.000s 12947.132us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 401.000s 12947.132us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 18.539us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 2.000s 13.223us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.000s 101.747us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.000s 101.747us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 173.174us 1 1 100.00
hmac_csr_rw 1.000s 34.184us 1 1 100.00
hmac_csr_aliasing 3.000s 695.501us 1 1 100.00
hmac_same_csr_outstanding 1.000s 103.704us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 173.174us 1 1 100.00
hmac_csr_rw 1.000s 34.184us 1 1 100.00
hmac_csr_aliasing 3.000s 695.501us 1 1 100.00
hmac_same_csr_outstanding 1.000s 103.704us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 64.047us 1 1 100.00
hmac_tl_intg_err 2.000s 192.496us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.000s 192.496us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 10.000s 1035.260us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 6.000s 2376.947us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 88.000s 10333.457us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.000s 109.237us 1 1 100.00