Simulation Results

Simulation Results: i2c

06/08/2026 19:53:31 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.89 %

code
86.63 %

assert
97.46 %

func
79.57 %

block
96.35 %

line
95.79 %

branch
93.50 %

toggle
72.35 %

FSM
84.89 %

Validation stages

V1		100.00%
V2		80.49%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	97.000s	6741.465us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	7.000s	560.543us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.000s	64.211us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	48.286us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	5.000s	3563.074us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	51.314us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.000s	18.571us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	48.286us	1	1	100.00
	i2c_csr_aliasing	2.000s	51.314us	1	1	100.00

33/41 passed

80.49 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.000s	54.743us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	2.000s	73.706us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	611.000s	2844.231us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	2.000s	27.240us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3600.000s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	1657.000s	3140.528us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	278.058us	1	1	100.00
	i2c_host_fifo_fmt_empty	11.000s	925.025us	1	1	100.00
	i2c_host_fifo_reset_rx	7.000s	165.228us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	200.000s	2526.314us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	11.000s	898.937us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.000s	15.660us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	4.000s	477.393us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	356.000s	102810.303us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	6.000s	543.460us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	25.000s	1653.094us	1	1	100.00
	i2c_target_intr_smoke	5.000s	1443.808us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	115.888us	1	1	100.00
	i2c_target_fifo_reset_tx	1.000s	223.256us	1	1	100.00
target_fifo_full				1	3	33.33
	i2c_target_stress_wr	3600.000s	0.000us	0	1	0.00
	i2c_target_stress_rd	25.000s	1653.094us	1	1	100.00
	i2c_target_intr_stress_wr	3600.000s	0.000us	0	1	0.00
target_timeout				1	1	100.00
	i2c_target_timeout	6.000s	7694.479us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	9.000s	4412.696us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	6.000s	538.620us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	10.000s	10848.866us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	5.000s	537.103us	1	1	100.00
	i2c_target_fifo_watermarks_tx	3.000s	138.871us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	611.000s	2844.231us	1	1	100.00
	i2c_host_perf_precise	2.000s	266.875us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	11.000s	898.937us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	5.000s	261.419us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	5.000s	1332.868us	1	1	100.00
	i2c_target_nack_acqfull_addr	3.000s	2555.842us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	261.972us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	4.000s	1286.934us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	3.000s	1822.480us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	2.000s	18.046us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	2.000s	31.619us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.000s	259.601us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.000s	259.601us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	64.211us	1	1	100.00
	i2c_csr_rw	1.000s	48.286us	1	1	100.00
	i2c_csr_aliasing	2.000s	51.314us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	97.391us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	64.211us	1	1	100.00
	i2c_csr_rw	1.000s	48.286us	1	1	100.00
	i2c_csr_aliasing	2.000s	51.314us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	97.391us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	3.000s	440.345us	1	1	100.00
	i2c_sec_cm	1.000s	41.944us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	3.000s	440.345us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	25.000s	2891.929us	1
target_error_intr				1
	i2c_target_unexp_stop	2.000s	1681.125us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	11.000s	3853.072us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				3 test runs
	i2c_host_fifo_watermark	41627603309432062836572870459099935012674005611663576118156067704629521566630	None
	i2c_target_stress_wr	111883126894650875961646597880196296215962576338752174189359507966951432057745	None
	i2c_target_intr_stress_wr	78249171065098068413552407081242955847377235108414692022892348102526433265413	None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				3 test runs
	i2c_host_error_intr	38686643369795197668896789855861669344538396012411244565357646729065065142144	97	UVM_INFO @ 54742573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	43659150874527528466306748064526480122302481790613101902957104348529777247042	95	UVM_INFO @ 73706370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_mode_toggle	52795642172974455517472740378146858649731117688955113086238709935565651198195	90	UVM_INFO @ 15659870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	57420150053483307335720705425575351107870632513763860465402637787548213461108	105	UVM_INFO @ 2891928744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	110527991324080783376634723274187418223610790058904884966831941586045626399696	100	UVM_INFO @ 3853071932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	49843085015723485412866779980310055750388492014423552529301080280537803262872	93	UVM_INFO @ 477392646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])				1 test run
	i2c_target_unexp_stop	29477089764617516539268643470530945641122577633481218002500696487565866191037	87	UVM_INFO @ 1681125063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	40974000914627875916313613381435025962696218550579384314051769705975269218764	88	UVM_INFO @ 10848866240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---