Simulation Results: lc_ctrl/volatile_unlock_disabled

 
06/08/2026 19:53:31 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.35 %
  • code
  • 92.69 %
  • assert
  • 95.97 %
  • func
  • 88.39 %
  • block
  • 96.52 %
  • line
  • 97.23 %
  • branch
  • 91.15 %
  • toggle
  • 87.16 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
93.33%
V2S
90.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 251.886us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 41.300us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 62.291us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 64.538us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 29.468us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 314.064us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 62.291us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 29.468us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 76.355us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.000s 441.854us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 19.827us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 45.721us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 2928.089us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.000s 486.591us 1 1 100.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 4.000s 2928.089us 1 1 100.00
lc_ctrl_prog_failure 2.000s 45.721us 1 1 100.00
lc_ctrl_errors 6.000s 486.591us 1 1 100.00
lc_ctrl_security_escalation 4.000s 1109.297us 1 1 100.00
lc_ctrl_jtag_state_failure 2.000s 179.511us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.000s 3260.376us 1 1 100.00
lc_ctrl_jtag_errors 15.000s 5344.555us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 4.000s 1390.277us 1 1 100.00
lc_ctrl_jtag_state_post_trans 2.000s 297.775us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.000s 3260.376us 1 1 100.00
lc_ctrl_jtag_errors 15.000s 5344.555us 1 1 100.00
lc_ctrl_jtag_access 7.000s 3961.489us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.000s 1406.975us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 293.335us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 373.685us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.000s 537.918us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.000s 951.036us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 16.797us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 167.221us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 40.214us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.000s 813.262us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 36.813us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 45.000s 10275.862us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 25.545us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 316.783us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 316.783us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 41.300us 1 1 100.00
lc_ctrl_csr_rw 2.000s 62.291us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 29.468us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 52.116us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 41.300us 1 1 100.00
lc_ctrl_csr_rw 2.000s 62.291us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 29.468us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 52.116us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 303.988us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 85.293us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 85.293us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.000s 441.854us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 2928.089us 1 1 100.00
lc_ctrl_sec_cm 3.000s 303.988us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 2928.089us 1 1 100.00
lc_ctrl_sec_cm 3.000s 303.988us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 2928.089us 1 1 100.00
lc_ctrl_sec_cm 3.000s 303.988us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 2928.089us 1 1 100.00
lc_ctrl_sec_cm 3.000s 303.988us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 2928.089us 1 1 100.00
lc_ctrl_sec_cm 3.000s 303.988us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 2928.089us 1 1 100.00
lc_ctrl_sec_cm 3.000s 303.988us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 2928.089us 1 1 100.00
lc_ctrl_sec_cm 3.000s 303.988us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 2928.089us 1 1 100.00
lc_ctrl_sec_cm 3.000s 303.988us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.000s 1109.297us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 3.000s 76.355us 1 1 100.00
lc_ctrl_jtag_state_post_trans 2.000s 297.775us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 416.674us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 416.674us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 1191.615us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 3742.493us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 3742.493us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 10.000s 4798.136us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 2 test runs
lc_ctrl_jtag_state_failure 76925842269614468216055747853242236065484708696172611958301738094453292463560 177
UVM_INFO @ 179510747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 82311995796629377056117614660211539066184450492441723229326365135076891710768 180
UVM_INFO @ 297775002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---