Simulation Results: lc_ctrl/volatile_unlock_enabled

 
06/08/2026 19:53:31 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.55 %
  • code
  • 93.28 %
  • assert
  • 95.97 %
  • func
  • 88.39 %
  • block
  • 97.02 %
  • line
  • 97.60 %
  • branch
  • 92.45 %
  • toggle
  • 87.83 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 32.482us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 22.382us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 63.490us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 391.415us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 148.297us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 25.589us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 63.490us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 148.297us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 740.954us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 358.092us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 20.585us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 58.810us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 1251.492us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.000s 1732.575us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.000s 1251.492us 1 1 100.00
lc_ctrl_prog_failure 2.000s 58.810us 1 1 100.00
lc_ctrl_errors 5.000s 1732.575us 1 1 100.00
lc_ctrl_security_escalation 5.000s 651.235us 1 1 100.00
lc_ctrl_jtag_state_failure 13.000s 1420.306us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.000s 300.742us 1 1 100.00
lc_ctrl_jtag_errors 15.000s 10203.961us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 5.000s 521.487us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 439.569us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.000s 300.742us 1 1 100.00
lc_ctrl_jtag_errors 15.000s 10203.961us 1 1 100.00
lc_ctrl_jtag_access 4.000s 274.874us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.000s 5777.389us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.000s 707.444us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 584.098us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.000s 10731.229us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.000s 3813.891us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 35.555us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 467.890us 1 1 100.00
lc_ctrl_jtag_alert_test 1.000s 33.037us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 10.000s 6631.998us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 17.406us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 125.000s 52345.533us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 32.855us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 231.481us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 231.481us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 22.382us 1 1 100.00
lc_ctrl_csr_rw 2.000s 63.490us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 148.297us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 181.436us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 22.382us 1 1 100.00
lc_ctrl_csr_rw 2.000s 63.490us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 148.297us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 181.436us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 169.812us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 80.059us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 80.059us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 358.092us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1251.492us 1 1 100.00
lc_ctrl_sec_cm 3.000s 169.812us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1251.492us 1 1 100.00
lc_ctrl_sec_cm 3.000s 169.812us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 1251.492us 1 1 100.00
lc_ctrl_sec_cm 3.000s 169.812us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 1251.492us 1 1 100.00
lc_ctrl_sec_cm 3.000s 169.812us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1251.492us 1 1 100.00
lc_ctrl_sec_cm 3.000s 169.812us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1251.492us 1 1 100.00
lc_ctrl_sec_cm 3.000s 169.812us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1251.492us 1 1 100.00
lc_ctrl_sec_cm 3.000s 169.812us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 1251.492us 1 1 100.00
lc_ctrl_sec_cm 3.000s 169.812us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 651.235us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 740.954us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.000s 439.569us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 444.323us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 444.323us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 483.491us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.000s 853.925us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.000s 853.925us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 21.000s 2913.544us 1 1 100.00