Simulation Results: mbx

 
06/08/2026 19:53:31 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.26 %
  • code
  • 91.23 %
  • assert
  • 97.15 %
  • func
  • 85.41 %
  • block
  • 96.56 %
  • line
  • 96.57 %
  • branch
  • 90.99 %
  • toggle
  • 86.12 %
Validation stages
V1
100.00%
V2
72.73%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 40.000s 7172.484us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 22.973us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 25.760us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 3.000s 207.557us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 22.990us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
mbx_csr_mem_rw_with_rand_reset 1.000s 261.516us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 25.760us 1 1 100.00
mbx_csr_aliasing 2.000s 22.990us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 6.000s 532.627us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 2.000s 24.798us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 28.000s 3393.356us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 8.000s 976.208us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 14.911us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 19.109us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 3.000s 45.038us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 3.000s 45.038us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 22.973us 1 1 100.00
mbx_csr_rw 1.000s 25.760us 1 1 100.00
mbx_csr_aliasing 2.000s 22.990us 1 1 100.00
mbx_same_csr_outstanding 2.000s 36.856us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 22.973us 1 1 100.00
mbx_csr_rw 1.000s 25.760us 1 1 100.00
mbx_csr_aliasing 2.000s 22.990us 1 1 100.00
mbx_same_csr_outstanding 2.000s 36.856us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 3.000s 604.730us 1 1 100.00
mbx_sec_cm 1.000s 28.885us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched 1 test run
mbx_stress 93257559831321955222140835008100802690222163071542028885333783617726130945117 350
UVM_INFO @ 532627313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register 1 test run
mbx_stress_zero_delays 61223235365812739440128482800905308503912751713867366764004912146708362389935 89
UVM_INFO @ 24797690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:622) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 1 test run
mbx_tl_errors 94626220967989501823912054780154587914880528222025328951272236723121477799175 86
TL item was: req: (cip_tl_seq_item@18626) { a_addr: 'h5a54f114 a_data: 'hef9b2132 a_mask: 'h2 a_size: 'h1 a_param: 'h0 a_source: 'hb2 a_opcode: 'h1 a_user: 'h24253 d_param: 'h0 d_source: 'hb2 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 45037536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---