Simulation Results: otbn

 
06/08/2026 19:53:31 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.17 %
  • code
  • 86.24 %
  • assert
  • 89.80 %
  • func
  • 97.46 %
  • block
  • 99.28 %
  • line
  • 99.48 %
  • branch
  • 94.78 %
  • toggle
  • 84.49 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
92.86%
V2S
96.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 100.446us 1 1 100.00
single_binary 1 1 100.00
otbn_single 17.000s 32.302us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 43.705us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 5.000s 17.316us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 7.000s 231.380us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 21.289us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 5.000s 41.354us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 5.000s 17.316us 1 1 100.00
otbn_csr_aliasing 4.000s 21.289us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 63.000s 6066.521us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 49.000s 2330.892us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 33.000s 115.522us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 50.000s 549.717us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 74.000s 269.286us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 91.000s 334.412us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 12.000s 103.639us 1 1 100.00
zero_state_err_urnd 0 1 0.00
otbn_zero_state_err_urnd 5.000s 7.324us 0 1 0.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 13.000s 29.502us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 5.000s 30.022us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 5.000s 21.974us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 8.000s 406.799us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 8.000s 406.799us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 43.705us 1 1 100.00
otbn_csr_rw 5.000s 17.316us 1 1 100.00
otbn_csr_aliasing 4.000s 21.289us 1 1 100.00
otbn_same_csr_outstanding 4.000s 21.368us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 43.705us 1 1 100.00
otbn_csr_rw 5.000s 17.316us 1 1 100.00
otbn_csr_aliasing 4.000s 21.289us 1 1 100.00
otbn_same_csr_outstanding 4.000s 21.368us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 14.000s 32.863us 1 1 100.00
otbn_dmem_err 8.000s 21.486us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 9.000s 114.631us 1 1 100.00
otbn_controller_ispr_rdata_err 11.000s 107.967us 1 1 100.00
otbn_mac_bignum_acc_err 9.000s 206.035us 1 1 100.00
otbn_urnd_err 7.000s 24.028us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 5.000s 17.988us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 6.000s 19.924us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 26.501us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 546.000s 3486.257us 1 1 100.00
otbn_tl_intg_err 10.000s 131.497us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 23.000s 1008.586us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 546.000s 3486.257us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 546.000s 3486.257us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 100.446us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 8.000s 21.486us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 14.000s 32.863us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 10.000s 131.497us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 12.000s 103.639us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 14.000s 32.863us 1 1 100.00
otbn_dmem_err 8.000s 21.486us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 7.324us 0 1 0.00
otbn_illegal_mem_acc 5.000s 17.988us 1 1 100.00
otbn_sec_cm 546.000s 3486.257us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 546.000s 3486.257us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 17.000s 32.302us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 14.000s 32.863us 1 1 100.00
otbn_dmem_err 8.000s 21.486us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 7.324us 0 1 0.00
otbn_illegal_mem_acc 5.000s 17.988us 1 1 100.00
otbn_sec_cm 546.000s 3486.257us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 546.000s 3486.257us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 12.000s 103.639us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 14.000s 32.863us 1 1 100.00
otbn_dmem_err 8.000s 21.486us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 7.324us 0 1 0.00
otbn_illegal_mem_acc 5.000s 17.988us 1 1 100.00
otbn_sec_cm 546.000s 3486.257us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 546.000s 3486.257us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 17.000s 32.302us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 10.000s 185.847us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 8.000s 29.214us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 17.000s 81.365us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 17.000s 81.365us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 9.000s 65.893us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 546.000s 3486.257us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 546.000s 3486.257us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 9.000s 146.671us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 546.000s 3486.257us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 546.000s 3486.257us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 8.000s 191.829us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 8.000s 191.829us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 10.000s 25.392us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 17.000s 32.302us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 17.000s 32.302us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 17.000s 32.302us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 74.000s 269.286us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 17.000s 32.302us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 17.000s 32.302us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 6.000s 89.641us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 17.000s 32.302us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 546.000s 3486.257us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 102.000s 512.140us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 9.000s 66.929us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 68378177559011205247496469389857075986619061287848995752948892372150901103191 186
UVM_INFO @ 512139551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 1 test run
otbn_zero_state_err_urnd 970355758786695519493154057582560341066127983165098540871834553281244067543 112
UVM_ERROR @ 7323861 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 7323861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---