Simulation Results: otp_ctrl

 
06/08/2026 19:53:31 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.16 %
  • code
  • 71.04 %
  • assert
  • 93.66 %
  • func
  • 54.77 %
  • line
  • 87.35 %
  • branch
  • 83.61 %
  • cond
  • 85.55 %
  • toggle
  • 64.38 %
  • FSM
  • 34.33 %
Validation stages
V1
100.00%
V2
60.00%
V2S
55.56%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.610s 57.806us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 2.920s 119.257us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.920s 124.866us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.740s 178.254us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 3.700s 112.609us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 6.440s 464.470us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.390s 2026.658us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.740s 178.254us 1 1 100.00
otp_ctrl_csr_aliasing 6.440s 464.470us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.380s 630.089us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.710s 43.653us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 124.650s 46434.257us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 4.370s 501.202us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 3.040s 269.356us 0 1 0.00
otp_ctrl_check_fail 8.430s 3903.283us 0 1 0.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 3.680s 1546.223us 0 1 0.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 8.010s 4014.241us 0 1 0.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 2.860s 212.087us 1 1 100.00
lc_interactions 0 2 0.00
otp_ctrl_parallel_lc_req 12.180s 1045.498us 0 1 0.00
otp_ctrl_parallel_lc_esc 3.190s 535.933us 0 1 0.00
otp_dai_errors 0 1 0.00
otp_ctrl_dai_errs 9.300s 840.126us 0 1 0.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 10.790s 713.435us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 13.920s 1020.541us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 16.640s 2477.085us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.960s 738.010us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.020s 94.875us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 5.390s 207.429us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 5.390s 207.429us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.920s 124.866us 1 1 100.00
otp_ctrl_csr_rw 1.740s 178.254us 1 1 100.00
otp_ctrl_csr_aliasing 6.440s 464.470us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.090s 106.645us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.920s 124.866us 1 1 100.00
otp_ctrl_csr_rw 1.740s 178.254us 1 1 100.00
otp_ctrl_csr_aliasing 6.440s 464.470us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.090s 106.645us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 262.310s 68662.575us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 262.310s 68662.575us 1 1 100.00
otp_ctrl_tl_intg_err 11.410s 1590.840us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 262.310s 68662.575us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 262.310s 68662.575us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 11.410s 1590.840us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 2.920s 119.257us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 2.920s 119.257us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 262.310s 68662.575us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 262.310s 68662.575us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 262.310s 68662.575us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 262.310s 68662.575us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 262.310s 68662.575us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 262.310s 68662.575us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 262.310s 68662.575us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 262.310s 68662.575us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 262.310s 68662.575us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 262.310s 68662.575us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 262.310s 68662.575us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 262.310s 68662.575us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 262.310s 68662.575us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 262.310s 68662.575us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 262.310s 68662.575us 1 1 100.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.190s 535.933us 0 1 0.00
otp_ctrl_sec_cm 262.310s 68662.575us 1 1 100.00
sec_cm_lci_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 3.190s 535.933us 0 1 0.00
sec_cm_kdi_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 3.190s 535.933us 0 1 0.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.190s 535.933us 0 1 0.00
otp_ctrl_macro_errs 10.790s 713.435us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 3.190s 535.933us 0 1 0.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.190s 535.933us 0 1 0.00
otp_ctrl_sec_cm 262.310s 68662.575us 1 1 100.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.190s 535.933us 0 1 0.00
otp_ctrl_sec_cm 262.310s 68662.575us 1 1 100.00
sec_cm_lci_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 3.190s 535.933us 0 1 0.00
sec_cm_kdi_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 3.190s 535.933us 0 1 0.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.190s 535.933us 0 1 0.00
otp_ctrl_macro_errs 10.790s 713.435us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 3.190s 535.933us 0 1 0.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.190s 535.933us 0 1 0.00
otp_ctrl_sec_cm 262.310s 68662.575us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 4.370s 501.202us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 8.430s 3903.283us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 8.010s 4014.241us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 8.010s 4014.241us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 8.010s 4014.241us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 8.010s 4014.241us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 8.010s 4014.241us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 2.920s 119.257us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 8.010s 4014.241us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 2.920s 119.257us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 262.310s 68662.575us 1 1 100.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 3.680s 1546.223us 0 1 0.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 2.920s 119.257us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 2.920s 119.257us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 10.790s 713.435us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 70.150s 26175.097us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 5.960s 278.813us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 5 test runs
otp_ctrl_background_chks 113183678460068666715327756910625831692959835559541373130056923186039979433953 1264
UVM_INFO @ 269355515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 60648938048158933264204213718653416507771391710170693394083845569985565223246 1532
UVM_INFO @ 535932885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 55428761136819394856566442243704301925642277674114496344944021873078887843497 5561
UVM_INFO @ 4014240659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 94378757262585786509617951952366163005547113122018171185000752260801302391161 3490
UVM_INFO @ 3903283044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 28111805470159053935828058585140218816986663120480269541777919953122879054248 4225
UVM_INFO @ 278813481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 2 test runs
otp_ctrl_partition_walk 114160990958216406029308490033757789464936740881357773119680021780603833709142 160055
UVM_INFO @ 46434256928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 25794726244100185709672810277484157935022793052277100327588484209683947427384 3946
UVM_INFO @ 1546222761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 50638385545685746688579565436590434106999594057278160769806759505654320965054 89
UVM_INFO @ 26175096701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_parallel_lc_req 60276057413749051009390875245604302657561615697223214091445959082074818669180 9952
UVM_INFO @ 1045498075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:677) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 1 test run
otp_ctrl_dai_errs 96647547018334862538340979048399544260332412693566551565919926767369071882235 11726
UVM_INFO @ 840125774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---