Simulation Results: rom_ctrl/64kb

 
06/08/2026 19:53:31 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.89 %
  • code
  • 83.36 %
  • assert
  • 97.53 %
  • func
  • 94.77 %
  • block
  • 87.04 %
  • line
  • 86.31 %
  • branch
  • 86.36 %
  • toggle
  • 84.57 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.000s 3789.933us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.000s 62.925us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.000s 59.922us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 2.000s 80.333us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 61.650us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.000s 133.937us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 2.000s 59.922us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 61.650us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 61.052us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 53.600us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 4.000s 963.546us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 5.000s 571.732us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.000s 709.637us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.000s 51.350us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.000s 722.635us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.000s 722.635us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 62.925us 1 1 100.00
rom_ctrl_csr_rw 2.000s 59.922us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 61.650us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 143.190us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 62.925us 1 1 100.00
rom_ctrl_csr_rw 2.000s 59.922us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 61.650us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 143.190us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 30.427us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 8.000s 801.707us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 186.000s 1466.324us 1 1 100.00
rom_ctrl_tl_intg_err 21.000s 157.991us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 186.000s 1466.324us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 186.000s 1466.324us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 30.427us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 30.427us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 30.427us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 30.427us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 30.427us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 186.000s 1466.324us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 186.000s 1466.324us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.000s 3789.933us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.000s 3789.933us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.000s 3789.933us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 21.000s 157.991us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 30.427us 0 1 0.00
rom_ctrl_kmac_err_chk 6.000s 709.637us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 30.427us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 30.427us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 5.000s 30.427us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 8.000s 801.707us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 186.000s 1466.324us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 14.000s 1335.311us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 80177162555273962089865270161191677767292277038105139953098090880389193879255 88
UVM_INFO @ 963545849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:278) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.fsm_vif.get_fsm_state() == rom_ctrl_pkg::ReadingLow) 1 test run
rom_ctrl_corrupt_sig_fatal_chk 10465298772229111804915715832962777461226383117830647990251155888304889369778 90
UVM_INFO @ 30427205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---