Simulation Results: rstmgr

 
06/08/2026 19:53:31 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.35 %
  • code
  • 99.05 %
  • assert
  • 98.72 %
  • func
  • 97.29 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 97.84 %
  • toggle
  • 99.43 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.190s 59.687us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.070s 93.385us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.260s 36.985us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.500s 120.150us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.150s 37.956us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.090s 65.577us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.260s 36.985us 1 1 100.00
rstmgr_csr_aliasing 1.150s 37.956us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.410s 127.719us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.970s 38.441us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.930s 55.433us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 7.430s 979.693us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 7.430s 979.693us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 7.430s 979.693us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 7.430s 979.693us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 14.490s 2184.815us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.830s 36.103us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.680s 58.776us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.680s 58.776us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.070s 93.385us 1 1 100.00
rstmgr_csr_rw 1.260s 36.985us 1 1 100.00
rstmgr_csr_aliasing 1.150s 37.956us 1 1 100.00
rstmgr_same_csr_outstanding 0.830s 37.403us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.070s 93.385us 1 1 100.00
rstmgr_csr_rw 1.260s 36.985us 1 1 100.00
rstmgr_csr_aliasing 1.150s 37.956us 1 1 100.00
rstmgr_same_csr_outstanding 0.830s 37.403us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 29.800s 6892.338us 1 1 100.00
rstmgr_tl_intg_err 4.000s 326.916us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 29.800s 6892.338us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 29.800s 6892.338us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 4.000s 326.916us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.080s 63.264us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.350s 424.928us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.970s 292.225us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 29.800s 6892.338us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.260s 36.985us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.260s 36.985us 1 1 100.00