Simulation Results: rstmgr_cnsty_chk

 
06/08/2026 19:53:31 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: vcs [unknown]
Validation stages
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rstmgr_cnsty_chk_test 2.810s 9812.290us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == *)) 1 test run
rstmgr_cnsty_chk_test 28700052768115646515066086578565806504362408847699620713011728871293721169481 175
UVM_INFO @ 1880430312 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16
UVM_INFO @ 1899150312 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16
UVM_INFO @ 1917870312 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16
UVM_INFO @ 1936590312 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16
Job cancelled because all of its dependencies failed or were killed. 1 test run
rstmgr_cnsty_chk None None
Job cancelled because one of its dependencies failed or was killed. 1 test run
rstmgr_cnsty_chk None None