Simulation Results

Simulation Results: rv_dm/use_dmi_interface

06/08/2026 19:53:31 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.70 %

code
73.66 %

assert
96.59 %

func
92.86 %

block
89.75 %

line
89.52 %

branch
72.17 %

toggle
70.45 %

FSM
62.50 %

Validation stages

V1		96.30%
V2		69.57%
V2S		100.00%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	34.000s	2497.401us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	32.000s	592.998us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	30.000s	123.304us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	42.000s	42686.347us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	29.000s	888.582us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	46.000s	12325.294us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	31.000s	981.883us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	29.000s	60.826us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	67.000s	38463.828us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	30.000s	271.227us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	34.000s	128.452us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	31.000s	486.270us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	30.000s	174.229us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	30.000s	235.375us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	31.000s	157.235us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	30.000s	180.603us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	32.000s	1442.986us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	30.000s	271.227us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	31.000s	363.357us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	30.000s	356.362us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	31.000s	486.270us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	31.000s	156.448us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	33.000s	114.999us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	31.000s	123.060us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	62.000s	4424.864us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	44.000s	614.236us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	31.000s	263.530us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	44.000s	614.236us	1	1	100.00
	rv_dm_csr_rw	31.000s	123.060us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	29.000s	58.010us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	29.000s	187.514us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	34.000s	2497.401us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	30.000s	389.441us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	30.000s	108.016us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	30.000s	253.438us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	35.000s	2342.196us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	31.000s	684.990us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	34.000s	1099.580us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	35.000s	20313.821us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	36.000s	4109.942us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	31.000s	532.239us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	32.000s	2010.585us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	32.000s	154.470us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	31.000s	64.239us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	36.000s	9092.667us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	79.000s	3530.810us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	30.000s	314.042us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	31.000s	1075.683us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	29.000s	145.851us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	30.000s	476.800us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	30.000s	476.800us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	44.000s	614.236us	1	1	100.00
	rv_dm_csr_hw_reset	33.000s	114.999us	1	1	100.00
	rv_dm_csr_rw	31.000s	123.060us	1	1	100.00
	rv_dm_same_csr_outstanding	32.000s	336.210us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	44.000s	614.236us	1	1	100.00
	rv_dm_csr_hw_reset	33.000s	114.999us	1	1	100.00
	rv_dm_csr_rw	31.000s	123.060us	1	1	100.00
	rv_dm_same_csr_outstanding	32.000s	336.210us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	30.000s	571.116us	1	1	100.00
	rv_dm_tl_intg_err	34.000s	3558.005us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	34.000s	3558.005us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	32.000s	2010.585us	1	1	100.00
	rv_dm_debug_disabled	31.000s	84.799us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	32.000s	2010.585us	1	1	100.00
	rv_dm_debug_disabled	31.000s	84.799us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	34.000s	2497.401us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	32.000s	316.055us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	29.000s	374.255us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	29.000s	374.255us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	32.000s	316.055us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	47.000s	6252.394us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	172.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				3 test runs
	rv_dm_sba_tl_access	112650351945752943974197481919160726407847994223727799842754441347297965039523	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23873
	rv_dm_bad_sba_tl_access	11043814088370313026676771748378896829848139403036709724168737094586519795755	117	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23922
	rv_dm_autoincr_sba_tl_access	33690809106234081075198088117704630501672091449838688475965016020413576345275	129	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23898
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				2 test runs
	rv_dm_jtag_dmi_debug_disabled	8041960211083591577287237463962046335077187607277498917337622053739246312290	87	UVM_INFO @ 532238827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	68505115796497586257279857929355267647139971972369510385348913893158737240317	89	UVM_INFO @ 1075683166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				1 test run
	rv_dm_delayed_resp_sba_tl_access	74104884499339297399061765381208667098573722126072265816669203247136930354089	107	UVM_INFO @ 1099580138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				1 test run
	rv_dm_mem_tl_access_resuming	57294036860778455450279654364154860416006617590353933715502746569767073379300	87	UVM_INFO @ 174229309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				1 test run
	rv_dm_hart_unavail	114346713671374511033639330145318239610986151737125882619216567340611836631222	87	UVM_INFO @ 64239076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	7598084776107373608539120072950112931842041917343043912706183629726852538929	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_dm_common_vseq] Check failed (vseq_done)				1 test run
	rv_dm_stress_all_with_rand_reset	115653631957635482502971353518660119781935303080721559097919298720914170930490	127	UVM_INFO @ 6252394310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---