Simulation Results: rv_timer

 
06/08/2026 19:53:31 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.97 %
  • code
  • 90.45 %
  • assert
  • 97.47 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 405.342us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 29.386us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 29.637us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 844.804us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 13.690us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 27.166us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 29.637us 1 1 100.00
rv_timer_csr_aliasing 1.000s 13.690us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 2.000s 583.580us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 2036.150us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 2.000s 95.027us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 2.000s 95.027us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.000s 2762.196us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 40.456us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 2.000s 25.805us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 196.307us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 196.307us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 29.386us 1 1 100.00
rv_timer_csr_rw 1.000s 29.637us 1 1 100.00
rv_timer_csr_aliasing 1.000s 13.690us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 107.724us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 29.386us 1 1 100.00
rv_timer_csr_rw 1.000s 29.637us 1 1 100.00
rv_timer_csr_aliasing 1.000s 13.690us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 107.724us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 135.355us 1 1 100.00
rv_timer_tl_intg_err 1.000s 96.869us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.000s 96.869us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.000s 132.889us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.000s 44.814us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 23.000s 3748.969us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 28752157993787132521737480732898968941696234422489213839655508625986205332145 88
UVM_INFO @ 132888700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 56417171648138622762758025615001614199742689668535374579013935550872331166928 84
UVM_INFO @ 583579690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 53054008517539243609292135179874725173961355986516866558564033887003075160517 85
UVM_INFO @ 44814434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---