Simulation Results: spi_device/1r1w

 
06/08/2026 19:53:31 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.17 %
  • code
  • 89.52 %
  • assert
  • 95.40 %
  • func
  • 67.61 %
  • block
  • 98.33 %
  • line
  • 98.75 %
  • branch
  • 96.98 %
  • toggle
  • 72.75 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 226.000s 127149.597us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 89.886us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.000s 141.829us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 19.000s 3726.655us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 8.000s 807.115us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 3.000s 204.548us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.000s 141.829us 1 1 100.00
spi_device_csr_aliasing 8.000s 807.115us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.000s 11.237us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 3.000s 66.611us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 19.393us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 1.000s 11.723us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 1.000s 4.497us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.000s 97.606us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.000s 97.606us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 9.000s 1978.824us 1 1 100.00
spi_device_tpm_sts_read 2.000s 67.227us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 1.000s 40.398us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 3.000s 64.320us 1 1 100.00
spi_device_flash_all 22.000s 1238.274us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 13.000s 5474.456us 1 1 100.00
spi_device_flash_all 22.000s 1238.274us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 13.000s 5474.456us 1 1 100.00
spi_device_flash_all 22.000s 1238.274us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 22.000s 1238.274us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 50.000s 3536.168us 1 1 100.00
spi_device_flash_all 22.000s 1238.274us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 50.000s 3536.168us 1 1 100.00
spi_device_flash_all 22.000s 1238.274us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 50.000s 3536.168us 1 1 100.00
spi_device_flash_all 22.000s 1238.274us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 50.000s 3536.168us 1 1 100.00
spi_device_flash_all 22.000s 1238.274us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 50.000s 3536.168us 1 1 100.00
spi_device_flash_all 22.000s 1238.274us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 7.000s 1410.928us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 14.000s 1130.381us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 14.000s 1130.381us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 14.000s 1130.381us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 3.000s 338.180us 1 1 100.00
spi_device_read_buffer_direct 5.000s 163.060us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 14.000s 1130.381us 1 1 100.00
spi_device_flash_all 22.000s 1238.274us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 22.000s 1238.274us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 22.000s 1238.274us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 4.000s 236.704us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 4.000s 236.704us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 2.000s 31.057us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 226.000s 127149.597us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 88.000s 4037.540us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 472.000s 41591.050us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 1.000s 57.002us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 2.000s 12.450us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 7.000s 186.391us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 7.000s 186.391us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 89.886us 1 1 100.00
spi_device_csr_rw 2.000s 141.829us 1 1 100.00
spi_device_csr_aliasing 8.000s 807.115us 1 1 100.00
spi_device_same_csr_outstanding 4.000s 742.948us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 89.886us 1 1 100.00
spi_device_csr_rw 2.000s 141.829us 1 1 100.00
spi_device_csr_aliasing 8.000s 807.115us 1 1 100.00
spi_device_same_csr_outstanding 4.000s 742.948us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 3.000s 540.452us 1 1 100.00
spi_device_tl_intg_err 14.000s 279.353us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 14.000s 279.353us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 56990606540500324479067188470557162343689863369225654339881393985879125376022 87
UVM_ERROR @ 9022570 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[974] not found within the scope .
UVM_ERROR @ 9022570 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[974] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 7134210575495162249887044295434128331565600180637243244971789915812557194127 85
UVM_ERROR @ 1959012 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe9 [11101001] vs 0x0 [0])
UVM_ERROR @ 2019012 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x371 [1101110001] vs 0x0 [0])
UVM_ERROR @ 2056012 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x18 [11000] vs 0x0 [0])
UVM_ERROR @ 2118012 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2e1 [1011100001] vs 0x0 [0])