Simulation Results: spi_host

 
06/08/2026 19:53:31 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.59 %
  • code
  • 91.25 %
  • assert
  • 95.27 %
  • func
  • 88.24 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 72.90 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 3.000s 475.017us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 30.802us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 29.279us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 265.372us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 165.524us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 26.649us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 29.279us 1 1 100.00
spi_host_csr_aliasing 1.000s 165.524us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 16.477us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 44.663us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 24.175us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 16.000s 494.355us 1 1 100.00
spi_host_error_cmd 1.000s 20.714us 1 1 100.00
spi_host_event 10.000s 1299.053us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 165.892us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 165.892us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 165.892us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 101.000s 6214.699us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 7.000s 350.639us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 96.517us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 165.892us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 165.892us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 3.000s 475.017us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 3.000s 475.017us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 12.000s 1310.797us 1 1 100.00
spien 1 1 100.00
spi_host_spien 181.000s 8892.096us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 88.000s 38909.515us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 257.940us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 16.000s 494.355us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 18.120us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 27.474us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 71.140us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 71.140us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 30.802us 1 1 100.00
spi_host_csr_rw 2.000s 29.279us 1 1 100.00
spi_host_csr_aliasing 1.000s 165.524us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 17.177us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 30.802us 1 1 100.00
spi_host_csr_rw 2.000s 29.279us 1 1 100.00
spi_host_csr_aliasing 1.000s 165.524us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 17.177us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 180.268us 1 1 100.00
spi_host_sec_cm 2.000s 105.618us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 180.268us 1 1 100.00