Simulation Results: sram_ctrl/main

 
06/08/2026 19:53:31 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.18 %
  • code
  • 96.79 %
  • assert
  • 97.55 %
  • func
  • 91.20 %
  • block
  • 96.09 %
  • line
  • 96.75 %
  • branch
  • 94.32 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 5638.608us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 25.956us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 52.869us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 130.747us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 37.709us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 356.298us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 52.869us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 37.709us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 120.000s 12921.839us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 117.000s 23652.910us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 15.000s 3341.858us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 66.000s 9870.278us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 141.000s 15336.326us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 27.000s 25042.350us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 9.000s 3349.583us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 16.000s 3865.377us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 676.878us 1 1 100.00
sram_ctrl_partial_access_b2b 177.000s 6937.613us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 5.000s 1362.358us 1 1 100.00
sram_ctrl_throughput_w_partial_write 3.000s 1334.734us 1 1 100.00
sram_ctrl_throughput_w_readback 6.000s 2800.405us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 8.000s 1392.222us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 356.066us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 216.000s 35806.750us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 80.615us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 368.998us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 368.998us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 25.956us 1 1 100.00
sram_ctrl_csr_rw 1.000s 52.869us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 37.709us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 44.739us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 25.956us 1 1 100.00
sram_ctrl_csr_rw 1.000s 52.869us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 37.709us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 44.739us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 14766.982us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 1047.535us 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 171.130us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 1047.535us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 171.130us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 1392.222us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 1392.222us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 52.869us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 16.000s 3865.377us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 16.000s 3865.377us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 16.000s 3865.377us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 9.000s 3349.583us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.000s 701.364us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 14766.982us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.000s 7391.302us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 5638.608us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 5638.608us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 16.000s 3865.377us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 1047.535us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 9.000s 3349.583us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 1047.535us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1047.535us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 5638.608us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1047.535us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 9.000s 529.918us 1 1 100.00