Simulation Results: sram_ctrl/ret

 
06/08/2026 19:53:31 DVSim: v1.50.0 sha: 377160a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.11 %
  • code
  • 83.40 %
  • assert
  • 97.94 %
  • func
  • 95.00 %
  • block
  • 93.88 %
  • line
  • 94.98 %
  • branch
  • 89.64 %
  • toggle
  • 82.29 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 64.629us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 23.095us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 16.078us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 34.507us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 22.474us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 50.978us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 16.078us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 22.474us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 9.000s 2837.898us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 5.000s 116.833us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 10.000s 3005.628us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 152.000s 12362.244us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 6.000s 2042.605us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 4.000s 555.383us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.000s 1975.636us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 5.000s 656.084us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 46.812us 1 1 100.00
sram_ctrl_partial_access_b2b 179.000s 18998.414us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 63.736us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 141.217us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 40.573us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 11.000s 3648.451us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 79.134us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 38.000s 3892.497us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 188.803us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 52.348us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 52.348us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 23.095us 1 1 100.00
sram_ctrl_csr_rw 1.000s 16.078us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 22.474us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 59.374us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 23.095us 1 1 100.00
sram_ctrl_csr_rw 1.000s 16.078us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 22.474us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 59.374us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 395.910us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 313.229us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1197.916us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 313.229us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1197.916us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 3648.451us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 3648.451us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 16.078us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 5.000s 656.084us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 5.000s 656.084us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 5.000s 656.084us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.000s 1975.636us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 770.870us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 395.910us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 631.696us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 64.629us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 64.629us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 5.000s 656.084us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 313.229us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.000s 1975.636us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 313.229us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 313.229us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 64.629us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 313.229us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 43.000s 36306.733us 1 1 100.00