Simulation Results: ac_range_check

 
10/08/2026 19:46:33 DVSim: v1.50.1 sha: af43bb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.03 %
  • code
  • 93.18 %
  • assert
  • 97.75 %
  • func
  • 58.16 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 81.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 28.000s 6901.244us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 47.000s 2531.912us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 40.303us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 46.887us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 31.000s 5497.174us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 17.000s 1150.012us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 26.279us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 46.887us 1 1 100.00
ac_range_check_csr_aliasing 17.000s 1150.012us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 50.878us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 25.000s 1449.955us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 172.000s 8772.665us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 20.417us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 1.000s 13.257us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 139.141us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 139.141us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 40.303us 1 1 100.00
ac_range_check_csr_rw 2.000s 46.887us 1 1 100.00
ac_range_check_csr_aliasing 17.000s 1150.012us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 54.433us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 40.303us 1 1 100.00
ac_range_check_csr_rw 2.000s 46.887us 1 1 100.00
ac_range_check_csr_aliasing 17.000s 1150.012us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 54.433us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 11.000s 1651.380us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 11.000s 1651.380us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 11.000s 1651.380us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 11.000s 1651.380us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 83.000s 10277.861us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 2.000s 43.681us 1 1 100.00
ac_range_check_tl_intg_err 9.000s 1716.970us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 276.000s 2881.236us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 28.000s 2971.007us 1 1 100.00